Study of Vacuum-Assisted Spin Coating of Polymer Liner for High-Aspect-Ratio Through-Silicon-Via Applications

This paper provides a new approach for the formation of polymer liner for low-$k$ high-aspect-ratio through-silicon-vias involved in via-last backside-via 3-D integration applications. The approach mentioned, referred to as vacuum-assisted spin coating technique in this paper, is formed by combining a conventional spin coating technique and a vacuum treatment. Silicon blind vias with a diameter of 6~ μ m} and an aspect ratio of ∼ 8 were conformably coated on their sidewall with polyimide liner with the minimum step coverage ∼ 30 % by this approach. Impacts of via geometric parameters and wafer sizes on step coverage were investigated. Electrical characteristics were evaluated with a trench capacitor structure of which the insulator layer was formed by the vacuum-assisted spin coating technique. The minimum capacitance density of 5.3 nF/cm² and the leakage current density of ∼ 3 nA/cm² at a biased voltage of 5 V were obtained. The proposed vacuum-assisted spin coating technique is a simple, feasible, and cost-effective approach for 3-D integration applications.