Abstract
DSP program's running efficiency on board is often lower than which via the software simulation during the program development, which is mainly resulted from the user's improper use and incomplete understanding of the cache-based memory. This paper took the TI TMS320C6455 DSP as an example, analyzed its two-level internal cache, and summarized the methods of code optimization. Processor can achieve its best performance when using these code optimization methods. At last, a specific algorithm application in radar signal processing is proposed. Experiment result shows that these optimization are efficient.
| Original language | English |
|---|---|
| Title of host publication | International Conference on Graphic and Image Processing, ICGIP 2012 |
| DOIs | |
| Publication status | Published - 2013 |
| Event | 4th International Conference on Graphic and Image Processing, ICGIP 2012 - Singapore, Singapore Duration: 6 Oct 2012 → 7 Oct 2012 |
Publication series
| Name | Proceedings of SPIE - The International Society for Optical Engineering |
|---|---|
| Volume | 8768 |
| ISSN (Print) | 0277-786X |
| ISSN (Electronic) | 1996-756X |
Conference
| Conference | 4th International Conference on Graphic and Image Processing, ICGIP 2012 |
|---|---|
| Country/Territory | Singapore |
| City | Singapore |
| Period | 6/10/12 → 7/10/12 |
Keywords
- C64x+
- Cache
- Code optimization
- DSP
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Xu, C., Li, C., & Tang, B. (2013). DSP Code optimization based on cache. In International Conference on Graphic and Image Processing, ICGIP 2012 Article 87682Q (Proceedings of SPIE - The International Society for Optical Engineering; Vol. 8768). https://doi.org/10.1117/12.2010893