Small area low power consumption mask ROM ASIC design

The ASIC design of a 4K bit mask-programmable CMOS ROM is introduced, and the ROM has a small area of 0.082 mm² with a power-delay product of 0.036 PJ/bit. The high packing density and the excellent power-delay product are achieved by using double well, single polysilicon, double metal 0.6 μm CMOS technology and a serial ROM cell structure. The power supply currents in active and quiescent modes are 1.2 mA and less than 0.1 μA at+5 V, respectively. Using a novel and simple sensitive amplifier/driver structure efficiently reduces the memory access time. The memory access time is 36 ns.