Small area low power consumption mask ROM ASIC design

Wei Cui; Yue Qiu Han; He Chen; Yun Li

Small area low power consumption mask ROM ASIC design

Wei Cui^*, Yue Qiu Han, He Chen, Yun Li

^*Corresponding author for this work

School of Information and Electronics

Beijing Institute of Technology

Research output: Contribution to journal › Article › peer-review

Abstract

The ASIC design of a 4K bit mask-programmable CMOS ROM is introduced, and the ROM has a small area of 0.082 mm² with a power-delay product of 0.036 PJ/bit. The high packing density and the excellent power-delay product are achieved by using double well, single polysilicon, double metal 0.6 μm CMOS technology and a serial ROM cell structure. The power supply currents in active and quiescent modes are 1.2 mA and less than 0.1 μA at+5 V, respectively. Using a novel and simple sensitive amplifier/driver structure efficiently reduces the memory access time. The memory access time is 36 ns.

Original language	English
Pages (from-to)	934-936
Number of pages	3
Journal	Tien Tzu Hsueh Pao/Acta Electronica Sinica
Volume	30
Issue number	6
Publication status	Published - Jun 2002

Keywords

CMOS technology
Decoder
Low consumption
ROM
Sense amplifier

Cite this

Cui, W., Han, Y. Q., Chen, H., & Li, Y. (2002). Small area low power consumption mask ROM ASIC design. Tien Tzu Hsueh Pao/Acta Electronica Sinica, 30(6), 934-936.

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keywords = "CMOS technology, Decoder, Low consumption, ROM, Sense amplifier",

author = "Wei Cui and Han, {Yue Qiu} and He Chen and Yun Li",

year = "2002",

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language = "English",

volume = "30",

pages = "934--936",

journal = "Tien Tzu Hsueh Pao/Acta Electronica Sinica",

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AU - Cui, Wei

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AU - Chen, He

AU - Li, Yun

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N2 - The ASIC design of a 4K bit mask-programmable CMOS ROM is introduced, and the ROM has a small area of 0.082 mm2 with a power-delay product of 0.036 PJ/bit. The high packing density and the excellent power-delay product are achieved by using double well, single polysilicon, double metal 0.6 μm CMOS technology and a serial ROM cell structure. The power supply currents in active and quiescent modes are 1.2 mA and less than 0.1 μA at+5 V, respectively. Using a novel and simple sensitive amplifier/driver structure efficiently reduces the memory access time. The memory access time is 36 ns.

AB - The ASIC design of a 4K bit mask-programmable CMOS ROM is introduced, and the ROM has a small area of 0.082 mm2 with a power-delay product of 0.036 PJ/bit. The high packing density and the excellent power-delay product are achieved by using double well, single polysilicon, double metal 0.6 μm CMOS technology and a serial ROM cell structure. The power supply currents in active and quiescent modes are 1.2 mA and less than 0.1 μA at+5 V, respectively. Using a novel and simple sensitive amplifier/driver structure efficiently reduces the memory access time. The memory access time is 36 ns.

KW - CMOS technology

KW - Decoder

KW - Low consumption

KW - ROM

KW - Sense amplifier

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JO - Tien Tzu Hsueh Pao/Acta Electronica Sinica

JF - Tien Tzu Hsueh Pao/Acta Electronica Sinica

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Small area low power consumption mask ROM ASIC design

Abstract

Keywords

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