Optimized shortest path algorithm for on-chip board processor in large scale networks

In this paper, we present TriBA (Triplet based) NoC (network on-chip) architecture with 40 nodes referred as TriBA-NoC. TriBA-NoC is implemented in a multi-core 40 tile DDR-3 hardware. The nodes in the TriBA-NoC are connected through recursive triplets. We carried out the performance analysis in network simulator (NS-3) using several perspectives. We adopted TR-132 shortest routing path algorithm with novel router architecture for TriBA-NoC systems. The results of average packet latency for various patterns of traffic of a 40-core TriBA-NoC model are demonstrated. The results of the proposed 40-core TriBA-NoC model achieved better performances while compared to the TriBA.