Optimized shortest path algorithm for on-chip board processor in large scale networks

Ameer N. Onaizah; Yuanqing Xia; Khurram Hussain; Abdullah Mohamed

doi:10.1016/j.ijleo.2022.170151

Optimized shortest path algorithm for on-chip board processor in large scale networks

Ameer N. Onaizah, Yuanqing Xia^*, Khurram Hussain, Abdullah Mohamed

^*Corresponding author for this work

School of Automation

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

In this paper, we present TriBA (Triplet based) NoC (network on-chip) architecture with 40 nodes referred as TriBA-NoC. TriBA-NoC is implemented in a multi-core 40 tile DDR-3 hardware. The nodes in the TriBA-NoC are connected through recursive triplets. We carried out the performance analysis in network simulator (NS-3) using several perspectives. We adopted TR-132 shortest routing path algorithm with novel router architecture for TriBA-NoC systems. The results of average packet latency for various patterns of traffic of a 40-core TriBA-NoC model are demonstrated. The results of the proposed 40-core TriBA-NoC model achieved better performances while compared to the TriBA.

Original language	English
Article number	170151
Journal	Optik
Volume	271
DOIs	https://doi.org/10.1016/j.ijleo.2022.170151
Publication status	Published - Dec 2022

Keywords

Latency
Multi-core DDR-3 processor
Network on-chip
Shortest path routing

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10.1016/j.ijleo.2022.170151

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title = "Optimized shortest path algorithm for on-chip board processor in large scale networks",

abstract = "In this paper, we present TriBA (Triplet based) NoC (network on-chip) architecture with 40 nodes referred as TriBA-NoC. TriBA-NoC is implemented in a multi-core 40 tile DDR-3 hardware. The nodes in the TriBA-NoC are connected through recursive triplets. We carried out the performance analysis in network simulator (NS-3) using several perspectives. We adopted TR-132 shortest routing path algorithm with novel router architecture for TriBA-NoC systems. The results of average packet latency for various patterns of traffic of a 40-core TriBA-NoC model are demonstrated. The results of the proposed 40-core TriBA-NoC model achieved better performances while compared to the TriBA.",

keywords = "Latency, Multi-core DDR-3 processor, Network on-chip, Shortest path routing",

author = "Onaizah, {Ameer N.} and Yuanqing Xia and Khurram Hussain and Abdullah Mohamed",

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year = "2022",

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doi = "10.1016/j.ijleo.2022.170151",

language = "English",

volume = "271",

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T1 - Optimized shortest path algorithm for on-chip board processor in large scale networks

AU - Onaizah, Ameer N.

AU - Xia, Yuanqing

AU - Hussain, Khurram

AU - Mohamed, Abdullah

PY - 2022/12

Y1 - 2022/12

N2 - In this paper, we present TriBA (Triplet based) NoC (network on-chip) architecture with 40 nodes referred as TriBA-NoC. TriBA-NoC is implemented in a multi-core 40 tile DDR-3 hardware. The nodes in the TriBA-NoC are connected through recursive triplets. We carried out the performance analysis in network simulator (NS-3) using several perspectives. We adopted TR-132 shortest routing path algorithm with novel router architecture for TriBA-NoC systems. The results of average packet latency for various patterns of traffic of a 40-core TriBA-NoC model are demonstrated. The results of the proposed 40-core TriBA-NoC model achieved better performances while compared to the TriBA.

AB - In this paper, we present TriBA (Triplet based) NoC (network on-chip) architecture with 40 nodes referred as TriBA-NoC. TriBA-NoC is implemented in a multi-core 40 tile DDR-3 hardware. The nodes in the TriBA-NoC are connected through recursive triplets. We carried out the performance analysis in network simulator (NS-3) using several perspectives. We adopted TR-132 shortest routing path algorithm with novel router architecture for TriBA-NoC systems. The results of average packet latency for various patterns of traffic of a 40-core TriBA-NoC model are demonstrated. The results of the proposed 40-core TriBA-NoC model achieved better performances while compared to the TriBA.

KW - Latency

KW - Multi-core DDR-3 processor

KW - Network on-chip

KW - Shortest path routing

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VL - 271

JO - Optik

JF - Optik

M1 - 170151

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Optimized shortest path algorithm for on-chip board processor in large scale networks

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Keywords

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