Optimized Implementation for Wave Digital Filter Based Circuit Emulation on FPGA

A binary tree representation is designed in this paper for optimization of wave digital filter (WDF) implementation. To achieve this, an equivalent WDF model of the original circuit is converted into abinary tree representation at first. This WDF binary tree can then be transformed to several topologies with the same implication, since the WDF adaptors have a symmetrical behavior on their ports. Because the WDF implementation is related to field programmable gate array (FPGA) resource usage and the cycle time of emulation, choosing a proper binary tree topology for WDF implementation can help balance the complexity and performance quality of an emulation system. Both WDF-FPGA emulation and HSpice simulation on the same circuit are tested. There is no significant difference between these two simulations. However, in terms of time consumption, the WDF-FPGA emulation has an advantage over the other. Our experiment also demonstrates that the optimized WDF-FPGA emulation has an acceptable accuracy and feasibility.