@inproceedings{3b83f6aefd1c498a90da096b1fba0122,
title = "Multichannel high-speed data caching system on FPGA for RAID storage",
abstract = "Channelization RAID storage system requests multichannel data transmission and high transmission bandwidth. We design a data caching system which is inserted between fore-end data source interface and the back-end RAID interface on a FPGA implementation. The caching system uses DDR3 as the external memory because of its large storage capacity and high storage rate. It uses a special channel management system and only needs three clock cycles to complete the read–write scheduling of different channels. The caching system provides the AXI4-Lite interface, so it can be dynamically configured by the AXI4-Lite bus. After testing, the caching system can satisfy the request of multichannel storage task.",
keywords = "Caching system, DDR3, FPGA, Multichannel",
author = "Haixin Wang and Xue Bai and Qiongzhi Wu",
note = "Publisher Copyright: {\textcopyright} Springer Nature Singapore Pte Ltd. 2020.; International Conference on Communications, Signal Processing, and Systems, CSPS 2018 ; Conference date: 14-07-2018 Through 16-07-2018",
year = "2020",
doi = "10.1007/978-981-13-6508-9_58",
language = "English",
isbn = "9789811365072",
series = "Lecture Notes in Electrical Engineering",
publisher = "Springer Verlag",
pages = "482--491",
editor = "Qilian Liang and Xin Liu and Zhenyu Na and Wei Wang and Jiasong Mu and Baoju Zhang",
booktitle = "Communications, Signal Processing, and Systems - Proceedings of the 2018 CSPS Volume 3",
address = "Germany",
}