Multichannel high-speed data caching system on FPGA for RAID storage

Haixin Wang; Xue Bai; Qiongzhi Wu

doi:10.1007/978-981-13-6508-9_58

Multichannel high-speed data caching system on FPGA for RAID storage

Haixin Wang, Xue Bai, Qiongzhi Wu^*

^*Corresponding author for this work

School of Integrated Circuits and Electronics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Channelization RAID storage system requests multichannel data transmission and high transmission bandwidth. We design a data caching system which is inserted between fore-end data source interface and the back-end RAID interface on a FPGA implementation. The caching system uses DDR3 as the external memory because of its large storage capacity and high storage rate. It uses a special channel management system and only needs three clock cycles to complete the read–write scheduling of different channels. The caching system provides the AXI4-Lite interface, so it can be dynamically configured by the AXI4-Lite bus. After testing, the caching system can satisfy the request of multichannel storage task.

Original language	English
Title of host publication	Communications, Signal Processing, and Systems - Proceedings of the 2018 CSPS Volume 3
Subtitle of host publication	Systems
Editors	Qilian Liang, Xin Liu, Zhenyu Na, Wei Wang, Jiasong Mu, Baoju Zhang
Publisher	Springer Verlag
Pages	482-491
Number of pages	10
ISBN (Print)	9789811365072
DOIs	https://doi.org/10.1007/978-981-13-6508-9_58
Publication status	Published - 2020
Event	International Conference on Communications, Signal Processing, and Systems, CSPS 2018 - Dalian, China Duration: 14 Jul 2018 → 16 Jul 2018

Publication series

Name	Lecture Notes in Electrical Engineering
Volume	517
ISSN (Print)	1876-1100
ISSN (Electronic)	1876-1119

Conference

Conference	International Conference on Communications, Signal Processing, and Systems, CSPS 2018
Country/Territory	China
City	Dalian
Period	14/07/18 → 16/07/18

Keywords

Caching system
DDR3
FPGA
Multichannel

Access to Document

10.1007/978-981-13-6508-9_58

Cite this

Wang, H., Bai, X., & Wu, Q. (2020). Multichannel high-speed data caching system on FPGA for RAID storage. In Q. Liang, X. Liu, Z. Na, W. Wang, J. Mu, & B. Zhang (Eds.), Communications, Signal Processing, and Systems - Proceedings of the 2018 CSPS Volume 3: Systems (pp. 482-491). (Lecture Notes in Electrical Engineering; Vol. 517). Springer Verlag. https://doi.org/10.1007/978-981-13-6508-9_58

Wang, Haixin ; Bai, Xue ; Wu, Qiongzhi. / Multichannel high-speed data caching system on FPGA for RAID storage. Communications, Signal Processing, and Systems - Proceedings of the 2018 CSPS Volume 3: Systems. editor / Qilian Liang ; Xin Liu ; Zhenyu Na ; Wei Wang ; Jiasong Mu ; Baoju Zhang. Springer Verlag, 2020. pp. 482-491 (Lecture Notes in Electrical Engineering).

@inproceedings{3b83f6aefd1c498a90da096b1fba0122,

title = "Multichannel high-speed data caching system on FPGA for RAID storage",

abstract = "Channelization RAID storage system requests multichannel data transmission and high transmission bandwidth. We design a data caching system which is inserted between fore-end data source interface and the back-end RAID interface on a FPGA implementation. The caching system uses DDR3 as the external memory because of its large storage capacity and high storage rate. It uses a special channel management system and only needs three clock cycles to complete the read–write scheduling of different channels. The caching system provides the AXI4-Lite interface, so it can be dynamically configured by the AXI4-Lite bus. After testing, the caching system can satisfy the request of multichannel storage task.",

keywords = "Caching system, DDR3, FPGA, Multichannel",

author = "Haixin Wang and Xue Bai and Qiongzhi Wu",

note = "Publisher Copyright: {\textcopyright} Springer Nature Singapore Pte Ltd. 2020.; International Conference on Communications, Signal Processing, and Systems, CSPS 2018 ; Conference date: 14-07-2018 Through 16-07-2018",

year = "2020",

doi = "10.1007/978-981-13-6508-9_58",

language = "English",

isbn = "9789811365072",

series = "Lecture Notes in Electrical Engineering",

publisher = "Springer Verlag",

pages = "482--491",

editor = "Qilian Liang and Xin Liu and Zhenyu Na and Wei Wang and Jiasong Mu and Baoju Zhang",

booktitle = "Communications, Signal Processing, and Systems - Proceedings of the 2018 CSPS Volume 3",

address = "Germany",

}

Wang, H, Bai, X & Wu, Q 2020, Multichannel high-speed data caching system on FPGA for RAID storage. in Q Liang, X Liu, Z Na, W Wang, J Mu & B Zhang (eds), Communications, Signal Processing, and Systems - Proceedings of the 2018 CSPS Volume 3: Systems. Lecture Notes in Electrical Engineering, vol. 517, Springer Verlag, pp. 482-491, International Conference on Communications, Signal Processing, and Systems, CSPS 2018, Dalian, China, 14/07/18. https://doi.org/10.1007/978-981-13-6508-9_58

Multichannel high-speed data caching system on FPGA for RAID storage. / Wang, Haixin; Bai, Xue; Wu, Qiongzhi.
Communications, Signal Processing, and Systems - Proceedings of the 2018 CSPS Volume 3: Systems. ed. / Qilian Liang; Xin Liu; Zhenyu Na; Wei Wang; Jiasong Mu; Baoju Zhang. Springer Verlag, 2020. p. 482-491 (Lecture Notes in Electrical Engineering; Vol. 517).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Multichannel high-speed data caching system on FPGA for RAID storage

AU - Wang, Haixin

AU - Bai, Xue

AU - Wu, Qiongzhi

N1 - Publisher Copyright: © Springer Nature Singapore Pte Ltd. 2020.

PY - 2020

Y1 - 2020

N2 - Channelization RAID storage system requests multichannel data transmission and high transmission bandwidth. We design a data caching system which is inserted between fore-end data source interface and the back-end RAID interface on a FPGA implementation. The caching system uses DDR3 as the external memory because of its large storage capacity and high storage rate. It uses a special channel management system and only needs three clock cycles to complete the read–write scheduling of different channels. The caching system provides the AXI4-Lite interface, so it can be dynamically configured by the AXI4-Lite bus. After testing, the caching system can satisfy the request of multichannel storage task.

AB - Channelization RAID storage system requests multichannel data transmission and high transmission bandwidth. We design a data caching system which is inserted between fore-end data source interface and the back-end RAID interface on a FPGA implementation. The caching system uses DDR3 as the external memory because of its large storage capacity and high storage rate. It uses a special channel management system and only needs three clock cycles to complete the read–write scheduling of different channels. The caching system provides the AXI4-Lite interface, so it can be dynamically configured by the AXI4-Lite bus. After testing, the caching system can satisfy the request of multichannel storage task.

KW - Caching system

KW - DDR3

KW - FPGA

KW - Multichannel

UR - http://www.scopus.com/inward/record.url?scp=85068400873&partnerID=8YFLogxK

U2 - 10.1007/978-981-13-6508-9_58

DO - 10.1007/978-981-13-6508-9_58

M3 - Conference contribution

AN - SCOPUS:85068400873

SN - 9789811365072

T3 - Lecture Notes in Electrical Engineering

SP - 482

EP - 491

BT - Communications, Signal Processing, and Systems - Proceedings of the 2018 CSPS Volume 3

A2 - Liang, Qilian

A2 - Liu, Xin

A2 - Na, Zhenyu

A2 - Wang, Wei

A2 - Mu, Jiasong

A2 - Zhang, Baoju

PB - Springer Verlag

T2 - International Conference on Communications, Signal Processing, and Systems, CSPS 2018

Y2 - 14 July 2018 through 16 July 2018

ER -

Multichannel high-speed data caching system on FPGA for RAID storage

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Keywords

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