Implementation of MPEG codec system based on FPGA and upper computer

Lei Ren, Linbo Tang, Ye Jin

科研成果: 书/报告/会议事项章节会议稿件同行评审

1 引用 (Scopus)

摘要

Due to the huge amount of calculations of video compression, its implementation needs the support of powerful computing capability. This article briefly describes the principles and key technologies of MPEG-1, and proposes an implementation method of MPEG-1 codec system based on FPGA and upper computer. The MPEG-1 encoding is implemented in FPGA, meanwhile, the adding of HDLC protocol to the compressed data is also finished in FPGA. The compressed code stream with HDLC protocol is transmitted by RS485 bus. Then the upper computer receives compressed code stream data by MPB202 card, which can parse data with HDLC protocol. Finally, the upper computer gets the compressed image data, decodes the compressed data and displays the image. After verification, the system can successfully realize the MPEG-1 encoding and decoding. This system can be used as a basic reference to a more advanced video compression system.

源语言英语
主期刊名Proceedings - 2013 International Conference on Computational and Information Sciences, ICCIS 2013
1827-1830
页数4
DOI
出版状态已出版 - 2013
活动2013 5th International Conference on Computational and Information Sciences, ICCIS 2013 - Shiyan, Hubei, 中国
期限: 21 6月 201323 6月 2013

出版系列

姓名Proceedings - 2013 International Conference on Computational and Information Sciences, ICCIS 2013

会议

会议2013 5th International Conference on Computational and Information Sciences, ICCIS 2013
国家/地区中国
Shiyan, Hubei
时期21/06/1323/06/13

指纹

探究 'Implementation of MPEG codec system based on FPGA and upper computer' 的科研主题。它们共同构成独一无二的指纹。

引用此