TY - JOUR
T1 - Fractional-N frequency synthesis
T2 - Overview and practical aspects with FIR-embedded design
AU - Rhee, Woogeun
AU - Xu, Ni
AU - Zhou, Bo
AU - Wang, Zhihua
PY - 2013/4
Y1 - 2013/4
N2 - This paper gives an overview of fractional-N phase-locked loops (PLLs) with practical design perspectives focusing on a ΔΣ modulation technique and a finite-impulse response (FIR) filtering method. Spur generation and nonlinearity issues in the ΔΣ fractional-N PLLs are discussed with simulation and hardware results. High-order ΔΣ modulation with FIR-embedded filtering is considered for low noise frequency generation. Also, various architectures of finite-modulo fractional-N PLLs are reviewed for alternative low cost design, and the FIR filtering technique is shown to be useful for spur reduction in the finite-modulo fractional-N PLL design.
AB - This paper gives an overview of fractional-N phase-locked loops (PLLs) with practical design perspectives focusing on a ΔΣ modulation technique and a finite-impulse response (FIR) filtering method. Spur generation and nonlinearity issues in the ΔΣ fractional-N PLLs are discussed with simulation and hardware results. High-order ΔΣ modulation with FIR-embedded filtering is considered for low noise frequency generation. Also, various architectures of finite-modulo fractional-N PLLs are reviewed for alternative low cost design, and the FIR filtering technique is shown to be useful for spur reduction in the finite-modulo fractional-N PLL design.
KW - CMOS integrated circuits
KW - Delta-sigma modulator
KW - Fractional-N
KW - Frequency synthesizer
KW - PLL
UR - http://www.scopus.com/inward/record.url?scp=84876932293&partnerID=8YFLogxK
U2 - 10.5573/JSTS.2013.13.2.170
DO - 10.5573/JSTS.2013.13.2.170
M3 - Article
AN - SCOPUS:84876932293
SN - 1598-1657
VL - 13
SP - 170
EP - 183
JO - Journal of Semiconductor Technology and Science
JF - Journal of Semiconductor Technology and Science
IS - 2
ER -