Abstract
This paper gives an overview of fractional-N phase-locked loops (PLLs) with practical design perspectives focusing on a ΔΣ modulation technique and a finite-impulse response (FIR) filtering method. Spur generation and nonlinearity issues in the ΔΣ fractional-N PLLs are discussed with simulation and hardware results. High-order ΔΣ modulation with FIR-embedded filtering is considered for low noise frequency generation. Also, various architectures of finite-modulo fractional-N PLLs are reviewed for alternative low cost design, and the FIR filtering technique is shown to be useful for spur reduction in the finite-modulo fractional-N PLL design.
Original language | English |
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Pages (from-to) | 170-183 |
Number of pages | 14 |
Journal | Journal of Semiconductor Technology and Science |
Volume | 13 |
Issue number | 2 |
DOIs | |
Publication status | Published - Apr 2013 |
Externally published | Yes |
Keywords
- CMOS integrated circuits
- Delta-sigma modulator
- Fractional-N
- Frequency synthesizer
- PLL