FPGA implement of rapid acquisition for DSSS

A new architecture to realize fast acquisition for DSSS signals is proposed. This method based on parallel search of Doppler and code phase makes acquisition time hold a constant value. This architecture utilizes duplicate design to realize FFT and IFFT, and calculates the FFT of local code by software and stores its conjugate in BPROM; block floating-point arithmetic is implemented to enhance the dynamic range and computation accuracy. The whole design is implemented with one chip of XC2V3000-4 FPGA. When working clock is 58.08 MHz and code acquisition precision is 1/4 chip, the acquisition time is 2.72 ms.