FPGA implement of rapid acquisition for DSSS

Zhihong Dong; Wei Cui

FPGA implement of rapid acquisition for DSSS

Zhihong Dong^*, Wei Cui

^*Corresponding author for this work

School of Information and Electronics

Beijing Institute of Technology

Research output: Contribution to journal › Article › peer-review

Abstract

A new architecture to realize fast acquisition for DSSS signals is proposed. This method based on parallel search of Doppler and code phase makes acquisition time hold a constant value. This architecture utilizes duplicate design to realize FFT and IFFT, and calculates the FFT of local code by software and stores its conjugate in BPROM; block floating-point arithmetic is implemented to enhance the dynamic range and computation accuracy. The whole design is implemented with one chip of XC2V3000-4 FPGA. When working clock is 58.08 MHz and code acquisition precision is 1/4 chip, the acquisition time is 2.72 ms.

Original language	English
Pages (from-to)	196-199
Number of pages	4
Journal	Yi Qi Yi Biao Xue Bao/Chinese Journal of Scientific Instrument
Volume	29
Issue number	SUPPL. 2
Publication status	Published - Aug 2008

Keywords

Direct sequence spread-spectrum signals
FPGA
Rapid acquisition

Cite this

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title = "FPGA implement of rapid acquisition for DSSS",

abstract = "A new architecture to realize fast acquisition for DSSS signals is proposed. This method based on parallel search of Doppler and code phase makes acquisition time hold a constant value. This architecture utilizes duplicate design to realize FFT and IFFT, and calculates the FFT of local code by software and stores its conjugate in BPROM; block floating-point arithmetic is implemented to enhance the dynamic range and computation accuracy. The whole design is implemented with one chip of XC2V3000-4 FPGA. When working clock is 58.08 MHz and code acquisition precision is 1/4 chip, the acquisition time is 2.72 ms.",

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year = "2008",

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AB - A new architecture to realize fast acquisition for DSSS signals is proposed. This method based on parallel search of Doppler and code phase makes acquisition time hold a constant value. This architecture utilizes duplicate design to realize FFT and IFFT, and calculates the FFT of local code by software and stores its conjugate in BPROM; block floating-point arithmetic is implemented to enhance the dynamic range and computation accuracy. The whole design is implemented with one chip of XC2V3000-4 FPGA. When working clock is 58.08 MHz and code acquisition precision is 1/4 chip, the acquisition time is 2.72 ms.

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KW - FPGA

KW - Rapid acquisition

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JO - Yi Qi Yi Biao Xue Bao/Chinese Journal of Scientific Instrument

JF - Yi Qi Yi Biao Xue Bao/Chinese Journal of Scientific Instrument

IS - SUPPL. 2

ER -

FPGA implement of rapid acquisition for DSSS

Abstract

Keywords

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