摘要
This paper presents an improved 32-bit binary logarithm converter, which is optimized according to the characteristics of Xilinx Virtex4 series FPGA. The implementation in FPGA denotes that our improved method not only costs less resources but also has much higher speed. Meanwhile a novel and simple error correction method is proposed. It reduces the converter error to only one half of the Metchell's method. The analytical results of the approximation error are confirmed by numerical simulation results.
| 源语言 | 英语 |
|---|---|
| 主期刊名 | 2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008 |
| DOI | |
| 出版状态 | 已出版 - 2008 |
| 活动 | 2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008 - Dalian, 中国 期限: 12 10月 2008 → 14 10月 2008 |
出版系列
| 姓名 | 2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008 |
|---|
会议
| 会议 | 2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008 |
|---|---|
| 国家/地区 | 中国 |
| 市 | Dalian |
| 时期 | 12/10/08 → 14/10/08 |
指纹
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Zhijun, L., Jianping, A., Miao, Y., & Jing, Y. (2008). FPGA design and implementation of an improved 32-bit binary logarithm converter. 在 2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008 文章 4678466 (2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008). https://doi.org/10.1109/WiCom.2008.558