FPGA design and implementation of an improved 32-bit binary logarithm converter

Li Zhijun; An Jianping; Yang Miao; Yang Jing

doi:10.1109/WiCom.2008.558

FPGA design and implementation of an improved 32-bit binary logarithm converter

Li Zhijun^*, An Jianping, Yang Miao, Yang Jing

^*Corresponding author for this work

School of Cyberspace Science and Technology

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Citations (Scopus)

Abstract

This paper presents an improved 32-bit binary logarithm converter, which is optimized according to the characteristics of Xilinx Virtex4 series FPGA. The implementation in FPGA denotes that our improved method not only costs less resources but also has much higher speed. Meanwhile a novel and simple error correction method is proposed. It reduces the converter error to only one half of the Metchell's method. The analytical results of the approximation error are confirmed by numerical simulation results.

Original language	English
Title of host publication	2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008
DOIs	https://doi.org/10.1109/WiCom.2008.558
Publication status	Published - 2008
Event	2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008 - Dalian, China Duration: 12 Oct 2008 → 14 Oct 2008

Publication series

Name	2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008

Conference

Conference	2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008
Country/Territory	China
City	Dalian
Period	12/10/08 → 14/10/08

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10.1109/WiCom.2008.558

Cite this

Zhijun, L., Jianping, A., Miao, Y., & Jing, Y. (2008). FPGA design and implementation of an improved 32-bit binary logarithm converter. In 2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008 Article 4678466 (2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008). https://doi.org/10.1109/WiCom.2008.558

@inproceedings{2450d2fbe0004c439dda70886b430ddf,

title = "FPGA design and implementation of an improved 32-bit binary logarithm converter",

abstract = "This paper presents an improved 32-bit binary logarithm converter, which is optimized according to the characteristics of Xilinx Virtex4 series FPGA. The implementation in FPGA denotes that our improved method not only costs less resources but also has much higher speed. Meanwhile a novel and simple error correction method is proposed. It reduces the converter error to only one half of the Metchell's method. The analytical results of the approximation error are confirmed by numerical simulation results.",

author = "Li Zhijun and An Jianping and Yang Miao and Yang Jing",

year = "2008",

doi = "10.1109/WiCom.2008.558",

language = "English",

isbn = "9781424421084",

series = "2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008",

booktitle = "2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008",

note = "2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008 ; Conference date: 12-10-2008 Through 14-10-2008",

}

Zhijun, L, Jianping, A, Miao, Y & Jing, Y 2008, FPGA design and implementation of an improved 32-bit binary logarithm converter. in 2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008., 4678466, 2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008, 2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008, Dalian, China, 12/10/08. https://doi.org/10.1109/WiCom.2008.558

FPGA design and implementation of an improved 32-bit binary logarithm converter. / Zhijun, Li; Jianping, An; Miao, Yang et al.
2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008. 2008. 4678466 (2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - FPGA design and implementation of an improved 32-bit binary logarithm converter

AU - Zhijun, Li

AU - Jianping, An

AU - Miao, Yang

AU - Jing, Yang

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Y1 - 2008

N2 - This paper presents an improved 32-bit binary logarithm converter, which is optimized according to the characteristics of Xilinx Virtex4 series FPGA. The implementation in FPGA denotes that our improved method not only costs less resources but also has much higher speed. Meanwhile a novel and simple error correction method is proposed. It reduces the converter error to only one half of the Metchell's method. The analytical results of the approximation error are confirmed by numerical simulation results.

AB - This paper presents an improved 32-bit binary logarithm converter, which is optimized according to the characteristics of Xilinx Virtex4 series FPGA. The implementation in FPGA denotes that our improved method not only costs less resources but also has much higher speed. Meanwhile a novel and simple error correction method is proposed. It reduces the converter error to only one half of the Metchell's method. The analytical results of the approximation error are confirmed by numerical simulation results.

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DO - 10.1109/WiCom.2008.558

M3 - Conference contribution

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SN - 9781424421084

T3 - 2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008

BT - 2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008

T2 - 2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008

Y2 - 12 October 2008 through 14 October 2008

ER -

Zhijun L, Jianping A, Miao Y, Jing Y. FPGA design and implementation of an improved 32-bit binary logarithm converter. In 2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008. 2008. 4678466. (2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008). doi: 10.1109/WiCom.2008.558

FPGA design and implementation of an improved 32-bit binary logarithm converter

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