TY - GEN
T1 - FPGA design and implementation of an improved 32-bit binary logarithm converter
AU - Zhijun, Li
AU - Jianping, An
AU - Miao, Yang
AU - Jing, Yang
PY - 2008
Y1 - 2008
N2 - This paper presents an improved 32-bit binary logarithm converter, which is optimized according to the characteristics of Xilinx Virtex4 series FPGA. The implementation in FPGA denotes that our improved method not only costs less resources but also has much higher speed. Meanwhile a novel and simple error correction method is proposed. It reduces the converter error to only one half of the Metchell's method. The analytical results of the approximation error are confirmed by numerical simulation results.
AB - This paper presents an improved 32-bit binary logarithm converter, which is optimized according to the characteristics of Xilinx Virtex4 series FPGA. The implementation in FPGA denotes that our improved method not only costs less resources but also has much higher speed. Meanwhile a novel and simple error correction method is proposed. It reduces the converter error to only one half of the Metchell's method. The analytical results of the approximation error are confirmed by numerical simulation results.
UR - http://www.scopus.com/inward/record.url?scp=58049111092&partnerID=8YFLogxK
U2 - 10.1109/WiCom.2008.558
DO - 10.1109/WiCom.2008.558
M3 - Conference contribution
AN - SCOPUS:58049111092
SN - 9781424421084
T3 - 2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008
BT - 2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008
T2 - 2008 International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2008
Y2 - 12 October 2008 through 14 October 2008
ER -