FPGA-based accelerator for convolution operations

Yunfei Cao; Xin Wei; Tingting Qiao; He Chen

doi:10.1109/ICSIDP47821.2019.9172934

FPGA-based accelerator for convolution operations

Yunfei Cao, Xin Wei, Tingting Qiao, He Chen

信息与电子学院

Beijing Institute of Technology

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

6 引用（Scopus）

摘要

Convolutional neural networks have been widely used in many deep learning applications. Convolutional neural networks have a large number of convolution operations, which poses a huge challenge to real-time performance. In recent years, FPGA implementations of convolutional accelerators have received much attention due to their high performance and energy efficiency. In this paper, we implement an accelerator for convolution operations through the systolic array architecture on Xilinx ZedBoard device. The experimental results show that ours designed accelerators achieving performance density of up to 0.032 Gop/s/DSP.

源语言	英语
主期刊名	ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019
出版商	Institute of Electrical and Electronics Engineers Inc.
ISBN（电子版）	9781728123455
DOI	https://doi.org/10.1109/ICSIDP47821.2019.9172934
出版状态	已出版 - 12月 2019
活动	2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019 - Chongqing, 中国期限: 11 12月 2019 → 13 12月 2019

出版系列

姓名	ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019

会议

会议	2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019
国家/地区	中国
市	Chongqing
时期	11/12/19 → 13/12/19

联合国可持续发展目标

此成果有助于实现下列可持续发展目标：

访问文件

10.1109/ICSIDP47821.2019.9172934

其它文件与链接

链接到 Scopus 的出版物

引用此

Cao, Y., Wei, X., Qiao, T., & Chen, H. (2019). FPGA-based accelerator for convolution operations. 在 ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019 文章 9172934 (ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSIDP47821.2019.9172934

@inproceedings{1be94e1acc2d499e8121dafeec7c7098,

title = "FPGA-based accelerator for convolution operations",

abstract = "Convolutional neural networks have been widely used in many deep learning applications. Convolutional neural networks have a large number of convolution operations, which poses a huge challenge to real-time performance. In recent years, FPGA implementations of convolutional accelerators have received much attention due to their high performance and energy efficiency. In this paper, we implement an accelerator for convolution operations through the systolic array architecture on Xilinx ZedBoard device. The experimental results show that ours designed accelerators achieving performance density of up to 0.032 Gop/s/DSP.",

keywords = "Accelerator, CNN, FPGA, Systolic Array",

author = "Yunfei Cao and Xin Wei and Tingting Qiao and He Chen",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019 ; Conference date: 11-12-2019 Through 13-12-2019",

year = "2019",

month = dec,

doi = "10.1109/ICSIDP47821.2019.9172934",

language = "English",

series = "ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019",

address = "United States",

}

Cao, Y, Wei, X, Qiao, T & Chen, H 2019, FPGA-based accelerator for convolution operations. 在 ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019., 9172934, ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019, Chongqing, 中国, 11/12/19. https://doi.org/10.1109/ICSIDP47821.2019.9172934

FPGA-based accelerator for convolution operations. / Cao, Yunfei; Wei, Xin; Qiao, Tingting 等.
ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 9172934 (ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019).

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

TY - GEN

T1 - FPGA-based accelerator for convolution operations

AU - Cao, Yunfei

AU - Wei, Xin

AU - Qiao, Tingting

AU - Chen, He

PY - 2019/12

Y1 - 2019/12

N2 - Convolutional neural networks have been widely used in many deep learning applications. Convolutional neural networks have a large number of convolution operations, which poses a huge challenge to real-time performance. In recent years, FPGA implementations of convolutional accelerators have received much attention due to their high performance and energy efficiency. In this paper, we implement an accelerator for convolution operations through the systolic array architecture on Xilinx ZedBoard device. The experimental results show that ours designed accelerators achieving performance density of up to 0.032 Gop/s/DSP.

AB - Convolutional neural networks have been widely used in many deep learning applications. Convolutional neural networks have a large number of convolution operations, which poses a huge challenge to real-time performance. In recent years, FPGA implementations of convolutional accelerators have received much attention due to their high performance and energy efficiency. In this paper, we implement an accelerator for convolution operations through the systolic array architecture on Xilinx ZedBoard device. The experimental results show that ours designed accelerators achieving performance density of up to 0.032 Gop/s/DSP.

KW - Accelerator

KW - CNN

KW - FPGA

KW - Systolic Array

UR - http://www.scopus.com/inward/record.url?scp=85091932417&partnerID=8YFLogxK

U2 - 10.1109/ICSIDP47821.2019.9172934

DO - 10.1109/ICSIDP47821.2019.9172934

M3 - Conference contribution

AN - SCOPUS:85091932417

T3 - ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019

BT - ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019

Y2 - 11 December 2019 through 13 December 2019

ER -

Cao Y, Wei X, Qiao T, Chen H. FPGA-based accelerator for convolution operations. 在 ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 9172934. (ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019). doi: 10.1109/ICSIDP47821.2019.9172934

FPGA-based accelerator for convolution operations

摘要

出版系列

会议

联合国可持续发展目标

访问文件

其它文件与链接

指纹

引用此