@inproceedings{1be94e1acc2d499e8121dafeec7c7098,
title = "FPGA-based accelerator for convolution operations",
abstract = "Convolutional neural networks have been widely used in many deep learning applications. Convolutional neural networks have a large number of convolution operations, which poses a huge challenge to real-time performance. In recent years, FPGA implementations of convolutional accelerators have received much attention due to their high performance and energy efficiency. In this paper, we implement an accelerator for convolution operations through the systolic array architecture on Xilinx ZedBoard device. The experimental results show that ours designed accelerators achieving performance density of up to 0.032 Gop/s/DSP.",
keywords = "Accelerator, CNN, FPGA, Systolic Array",
author = "Yunfei Cao and Xin Wei and Tingting Qiao and He Chen",
note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019 ; Conference date: 11-12-2019 Through 13-12-2019",
year = "2019",
month = dec,
doi = "10.1109/ICSIDP47821.2019.9172934",
language = "English",
series = "ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019",
address = "United States",
}
