摘要
An approach of a low spurious, low phase noise, agile frequency synthesizer was presented. The synthesizer adopted DDS chip (AD9852) as the excitation for the PLL chip (Q3236) and TMS320C31 of TI as its control unit. By combining the Iutra-high frequency resolution of DDS and the high operation frequency of PLL, better performance can be achieved. The phase noise of the synthesizer output is less than-100 dB/Hz (away from carrier 1 kHz) and the spurious level is less than-60 dB.
源语言 | 英语 |
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页(从-至) | 753-756 |
页数 | 4 |
期刊 | Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology |
卷 | 21 |
期 | 6 |
出版状态 | 已出版 - 2001 |