Design and Implementation of High Performance FFT Processor with Radix-2^kAlgorithm

in this paper, a fixed-point pipelined fast Fourier transform (FFT) processor is designed with radix-2^kalgorithm and single-path delay feedback (SDF) architecture. Besides, the processor adopts a word length optimization strategy in order to reduce logic and memory resource utilization. Through this strategy, the word length required for each butterfly operation stage can be directly calculated and obtained by direct formula calculation without any experimental simulation, providing the theoretical basis for the word length configuration of the fixed-point pipelined FFT processor. The design and implementation results indicate that the fixed-point FFT processors employing the proposed word length configuration optimization strategy have significant advantages of lower logic resource occupation while ensuring the processing precision.