Design and Implementation of High Performance FFT Processor with Radix-2kAlgorithm

Long Pang; Yamei Huang; Chen Wang; Chen Yang; Yizhuang Xie; He Chen

doi:10.1109/ICSIDP47821.2019.9173055

Design and Implementation of High Performance FFT Processor with Radix-2^kAlgorithm

Long Pang, Yamei Huang, Chen Wang, Chen Yang, Yizhuang Xie, He Chen

School of Information and Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

in this paper, a fixed-point pipelined fast Fourier transform (FFT) processor is designed with radix-2^kalgorithm and single-path delay feedback (SDF) architecture. Besides, the processor adopts a word length optimization strategy in order to reduce logic and memory resource utilization. Through this strategy, the word length required for each butterfly operation stage can be directly calculated and obtained by direct formula calculation without any experimental simulation, providing the theoretical basis for the word length configuration of the fixed-point pipelined FFT processor. The design and implementation results indicate that the fixed-point FFT processors employing the proposed word length configuration optimization strategy have significant advantages of lower logic resource occupation while ensuring the processing precision.

Original language	English
Title of host publication	ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728123455
DOIs	https://doi.org/10.1109/ICSIDP47821.2019.9173055
Publication status	Published - Dec 2019
Event	2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019 - Chongqing, China Duration: 11 Dec 2019 → 13 Dec 2019

Publication series

Name	ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019

Conference

Conference	2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019
Country/Territory	China
City	Chongqing
Period	11/12/19 → 13/12/19

Keywords

fast Fourier transform
fixed-point
radix-2k
single-path delay feedback
word length configuration

Access to Document

10.1109/ICSIDP47821.2019.9173055

Cite this

Pang, L., Huang, Y., Wang, C., Yang, C., Xie, Y., & Chen, H. (2019). Design and Implementation of High Performance FFT Processor with Radix-2^kAlgorithm. In ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019 Article 9173055 (ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSIDP47821.2019.9173055

Pang, Long ; Huang, Yamei ; Wang, Chen et al. / Design and Implementation of High Performance FFT Processor with Radix-2^kAlgorithm. ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019).

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title = "Design and Implementation of High Performance FFT Processor with Radix-2kAlgorithm",

abstract = "in this paper, a fixed-point pipelined fast Fourier transform (FFT) processor is designed with radix-2kalgorithm and single-path delay feedback (SDF) architecture. Besides, the processor adopts a word length optimization strategy in order to reduce logic and memory resource utilization. Through this strategy, the word length required for each butterfly operation stage can be directly calculated and obtained by direct formula calculation without any experimental simulation, providing the theoretical basis for the word length configuration of the fixed-point pipelined FFT processor. The design and implementation results indicate that the fixed-point FFT processors employing the proposed word length configuration optimization strategy have significant advantages of lower logic resource occupation while ensuring the processing precision.",

keywords = "fast Fourier transform, fixed-point, radix-2k, single-path delay feedback, word length configuration",

author = "Long Pang and Yamei Huang and Chen Wang and Chen Yang and Yizhuang Xie and He Chen",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019 ; Conference date: 11-12-2019 Through 13-12-2019",

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series = "ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019",

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Pang, L, Huang, Y, Wang, C, Yang, C, Xie, Y & Chen, H 2019, Design and Implementation of High Performance FFT Processor with Radix-2^kAlgorithm. in ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019., 9173055, ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International Conference on Signal, Information and Data Processing, ICSIDP 2019, Chongqing, China, 11/12/19. https://doi.org/10.1109/ICSIDP47821.2019.9173055

Design and Implementation of High Performance FFT Processor with Radix-2^kAlgorithm. / Pang, Long; Huang, Yamei; Wang, Chen et al.
ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 9173055 (ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - in this paper, a fixed-point pipelined fast Fourier transform (FFT) processor is designed with radix-2kalgorithm and single-path delay feedback (SDF) architecture. Besides, the processor adopts a word length optimization strategy in order to reduce logic and memory resource utilization. Through this strategy, the word length required for each butterfly operation stage can be directly calculated and obtained by direct formula calculation without any experimental simulation, providing the theoretical basis for the word length configuration of the fixed-point pipelined FFT processor. The design and implementation results indicate that the fixed-point FFT processors employing the proposed word length configuration optimization strategy have significant advantages of lower logic resource occupation while ensuring the processing precision.

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Pang L, Huang Y, Wang C, Yang C, Xie Y , Chen H. Design and Implementation of High Performance FFT Processor with Radix-2^kAlgorithm. In ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 9173055. (ICSIDP 2019 - IEEE International Conference on Signal, Information and Data Processing 2019). doi: 10.1109/ICSIDP47821.2019.9173055