摘要
DDR SDRAM, with features of large capacity and high speed, has a good prospect in the acquisition of satellite navigation system which requires large amounts of data accumulation. Due to the particularity of the navigation signal processing algorithms, the time cannot be efficiently used during reading and writing in traditional design of DDR SDRAM controller, reducing the efficiency of data processing. This paper presents a new strategy of reading and writing and then implements a DDR SDRAM controller. Software simulation and hardware experimental tests prove the correctness and feasibility of this design.
| 源语言 | 英语 |
|---|---|
| 主期刊名 | ICSP 2012 - 2012 11th International Conference on Signal Processing, Proceedings |
| 页 | 456-460 |
| 页数 | 5 |
| DOI | |
| 出版状态 | 已出版 - 2012 |
| 活动 | 2012 11th International Conference on Signal Processing, ICSP 2012 - Beijing, 中国 期限: 21 10月 2012 → 25 10月 2012 |
出版系列
| 姓名 | International Conference on Signal Processing Proceedings, ICSP |
|---|---|
| 卷 | 1 |
会议
| 会议 | 2012 11th International Conference on Signal Processing, ICSP 2012 |
|---|---|
| 国家/地区 | 中国 |
| 市 | Beijing |
| 时期 | 21/10/12 → 25/10/12 |
指纹
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Wang, L., Wang, J., & Zhang, Q. (2012). Design and implementation of DDR SDRAM controller based on FPGA in satellite navigation system. 在 ICSP 2012 - 2012 11th International Conference on Signal Processing, Proceedings (页码 456-460). 文章 6491523 (International Conference on Signal Processing Proceedings, ICSP; 卷 1). https://doi.org/10.1109/ICoSP.2012.6491523