TY - GEN
T1 - Design and implementation of DDR SDRAM controller based on FPGA in satellite navigation system
AU - Wang, Li
AU - Wang, Ju
AU - Zhang, Qian
PY - 2012
Y1 - 2012
N2 - DDR SDRAM, with features of large capacity and high speed, has a good prospect in the acquisition of satellite navigation system which requires large amounts of data accumulation. Due to the particularity of the navigation signal processing algorithms, the time cannot be efficiently used during reading and writing in traditional design of DDR SDRAM controller, reducing the efficiency of data processing. This paper presents a new strategy of reading and writing and then implements a DDR SDRAM controller. Software simulation and hardware experimental tests prove the correctness and feasibility of this design.
AB - DDR SDRAM, with features of large capacity and high speed, has a good prospect in the acquisition of satellite navigation system which requires large amounts of data accumulation. Due to the particularity of the navigation signal processing algorithms, the time cannot be efficiently used during reading and writing in traditional design of DDR SDRAM controller, reducing the efficiency of data processing. This paper presents a new strategy of reading and writing and then implements a DDR SDRAM controller. Software simulation and hardware experimental tests prove the correctness and feasibility of this design.
KW - Controller
KW - DDR SDRAM
KW - FPGA
KW - Satellite navigation
UR - http://www.scopus.com/inward/record.url?scp=84876492923&partnerID=8YFLogxK
U2 - 10.1109/ICoSP.2012.6491523
DO - 10.1109/ICoSP.2012.6491523
M3 - Conference contribution
AN - SCOPUS:84876492923
SN - 9781467321945
T3 - International Conference on Signal Processing Proceedings, ICSP
SP - 456
EP - 460
BT - ICSP 2012 - 2012 11th International Conference on Signal Processing, Proceedings
T2 - 2012 11th International Conference on Signal Processing, ICSP 2012
Y2 - 21 October 2012 through 25 October 2012
ER -