Abstract
DDR SDRAM, with features of large capacity and high speed, has a good prospect in the acquisition of satellite navigation system which requires large amounts of data accumulation. Due to the particularity of the navigation signal processing algorithms, the time cannot be efficiently used during reading and writing in traditional design of DDR SDRAM controller, reducing the efficiency of data processing. This paper presents a new strategy of reading and writing and then implements a DDR SDRAM controller. Software simulation and hardware experimental tests prove the correctness and feasibility of this design.
| Original language | English |
|---|---|
| Title of host publication | ICSP 2012 - 2012 11th International Conference on Signal Processing, Proceedings |
| Pages | 456-460 |
| Number of pages | 5 |
| DOIs | |
| Publication status | Published - 2012 |
| Event | 2012 11th International Conference on Signal Processing, ICSP 2012 - Beijing, China Duration: 21 Oct 2012 → 25 Oct 2012 |
Publication series
| Name | International Conference on Signal Processing Proceedings, ICSP |
|---|---|
| Volume | 1 |
Conference
| Conference | 2012 11th International Conference on Signal Processing, ICSP 2012 |
|---|---|
| Country/Territory | China |
| City | Beijing |
| Period | 21/10/12 → 25/10/12 |
Keywords
- Controller
- DDR SDRAM
- FPGA
- Satellite navigation
Fingerprint
Dive into the research topics of 'Design and implementation of DDR SDRAM controller based on FPGA in satellite navigation system'. Together they form a unique fingerprint.Cite this
Wang, L., Wang, J., & Zhang, Q. (2012). Design and implementation of DDR SDRAM controller based on FPGA in satellite navigation system. In ICSP 2012 - 2012 11th International Conference on Signal Processing, Proceedings (pp. 456-460). Article 6491523 (International Conference on Signal Processing Proceedings, ICSP; Vol. 1). https://doi.org/10.1109/ICoSP.2012.6491523