Design and implementation of a processor for radar signal reconnaissance

Investigates a signal processor of electromic warefare (EW) digital receiver based on FFT/IFFT algorithm, and realized completely by FPGA constructed annularly. Four FPGAs implement respectively the high-speed data transmission interface, FFT/IFFT operation and signal detection in the time/frequency domain. The FPGAs run with distributed, multi-bus, parallel and pipeline mode. This processor can detect the parameters of carrier frequency and pulse description word for 4 simultaneous-arrival signals at most, and they need only about 20 ms to detect 4 signals while 256 K (1 K=1024) point FFT and 32 K point IFFT are adopted. The data receiving, operating and signal detection in time/frequency domain are realized on a board.