Design and implementation of a processor for radar signal reconnaissance

Yue Dong Luo; He Chen; Xiao Jun Wang

Design and implementation of a processor for radar signal reconnaissance

Yue Dong Luo^*, He Chen, Xiao Jun Wang

^*Corresponding author for this work

School of Information and Electronics

Beijing Institute of Technology

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

Investigates a signal processor of electromic warefare (EW) digital receiver based on FFT/IFFT algorithm, and realized completely by FPGA constructed annularly. Four FPGAs implement respectively the high-speed data transmission interface, FFT/IFFT operation and signal detection in the time/frequency domain. The FPGAs run with distributed, multi-bus, parallel and pipeline mode. This processor can detect the parameters of carrier frequency and pulse description word for 4 simultaneous-arrival signals at most, and they need only about 20 ms to detect 4 signals while 256 K (1 K=1024) point FFT and 32 K point IFFT are adopted. The data receiving, operating and signal detection in time/frequency domain are realized on a board.

Original language	English
Pages (from-to)	352-355
Number of pages	4
Journal	Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology
Volume	28
Issue number	4
Publication status	Published - Apr 2008

Keywords

Digital receiver
Fast Fourier transform (FFT)
Field programmable gate array (FPGA)
Signal processor

Cite this

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abstract = "Investigates a signal processor of electromic warefare (EW) digital receiver based on FFT/IFFT algorithm, and realized completely by FPGA constructed annularly. Four FPGAs implement respectively the high-speed data transmission interface, FFT/IFFT operation and signal detection in the time/frequency domain. The FPGAs run with distributed, multi-bus, parallel and pipeline mode. This processor can detect the parameters of carrier frequency and pulse description word for 4 simultaneous-arrival signals at most, and they need only about 20 ms to detect 4 signals while 256 K (1 K=1024) point FFT and 32 K point IFFT are adopted. The data receiving, operating and signal detection in time/frequency domain are realized on a board.",

keywords = "Digital receiver, Fast Fourier transform (FFT), Field programmable gate array (FPGA), Signal processor",

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AB - Investigates a signal processor of electromic warefare (EW) digital receiver based on FFT/IFFT algorithm, and realized completely by FPGA constructed annularly. Four FPGAs implement respectively the high-speed data transmission interface, FFT/IFFT operation and signal detection in the time/frequency domain. The FPGAs run with distributed, multi-bus, parallel and pipeline mode. This processor can detect the parameters of carrier frequency and pulse description word for 4 simultaneous-arrival signals at most, and they need only about 20 ms to detect 4 signals while 256 K (1 K=1024) point FFT and 32 K point IFFT are adopted. The data receiving, operating and signal detection in time/frequency domain are realized on a board.

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KW - Fast Fourier transform (FFT)

KW - Field programmable gate array (FPGA)

KW - Signal processor

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Design and implementation of a processor for radar signal reconnaissance

Abstract

Keywords

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