Design and implementation of a pipeline processor for various-size FFTs

Zhen Bin Gao*, He Chen, Yue Qiu Han

*此作品的通讯作者

科研成果: 期刊稿件文章同行评审

4 引用 (Scopus)

摘要

A pipeline processor which may compute various 2n points FFT is proposed for continuously performing complex points fast Fourier transforms (FFTs). The processor consists of several stages of butterfly computational elements connected with ping-pang RAMs that reorder the data between the butterfly stages. By properly ordering the input data to the pipeline and addressing the twiddle factors ROM, and by controlling the stage's operating status, it is shown that any FFT whose sizes are powers of the pipeline's radix can be performed. Using block-floating point arithmetic, the processor can provide a high quality. The design is written in VHDL at RTL level, and implemented on a single FPGA chip. The processor can operate at 80 MHz, and compute a 1024 complex points FFT in 12.8 μs when operating continuously.

源语言英语
页(从-至)268-271
页数4
期刊Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology
25
3
出版状态已出版 - 3月 2005

指纹

探究 'Design and implementation of a pipeline processor for various-size FFTs' 的科研主题。它们共同构成独一无二的指纹。

引用此