Design and implementation of a pipeline processor for various-size FFTs

A pipeline processor which may compute various 2ⁿ points FFT is proposed for continuously performing complex points fast Fourier transforms (FFTs). The processor consists of several stages of butterfly computational elements connected with ping-pang RAMs that reorder the data between the butterfly stages. By properly ordering the input data to the pipeline and addressing the twiddle factors ROM, and by controlling the stage's operating status, it is shown that any FFT whose sizes are powers of the pipeline's radix can be performed. Using block-floating point arithmetic, the processor can provide a high quality. The design is written in VHDL at RTL level, and implemented on a single FPGA chip. The processor can operate at 80 MHz, and compute a 1024 complex points FFT in 12.8 μs when operating continuously.