ASIC design of high-speed low-power HDLC controller

Combined with the engineering requirement, a high-speed low-power ASIC (application specific integrated circuit) design of HDLC (high speed data link control) controller based on RS-485 bus is given. Based on the principle of top-Down design, this ASIC design uses multi-techniques to reduce its die area and dynamic power, and overcomes some problems appeared frequently in application of the RS-485 circuits formed by the standard interface chips. This design also improves the system reliability and reduces the system area.