Abstract
Combined with the engineering requirement, a high-speed low-power ASIC (application specific integrated circuit) design of HDLC (high speed data link control) controller based on RS-485 bus is given. Based on the principle of top-Down design, this ASIC design uses multi-techniques to reduce its die area and dynamic power, and overcomes some problems appeared frequently in application of the RS-485 circuits formed by the standard interface chips. This design also improves the system reliability and reduces the system area.
| Original language | English |
|---|---|
| Pages (from-to) | 66-69 |
| Number of pages | 4 |
| Journal | Journal of Beijing Institute of Technology (English Edition) |
| Volume | 12 |
| Issue number | SUPPL. |
| Publication status | Published - Dec 2003 |
Keywords
- Application specific integrated circuit
- Communication controller
- High speed data link control
- RS-485 bus
Fingerprint
Dive into the research topics of 'ASIC design of high-speed low-power HDLC controller'. Together they form a unique fingerprint.Cite this
Chen, H., & Han, Y. Q. (2003). ASIC design of high-speed low-power HDLC controller. Journal of Beijing Institute of Technology (English Edition), 12(SUPPL.), 66-69.