ASIC design of DA-based 2D inverse discrete cosine transform

The full top-down ASIC (application specific integrated circuits) design of 2D inverse discrete cosine transform (IDCT) was presented. In the 1D IDCT algorithm, the Chen-based fast IDCT algorithm was utilized, and multiplier accumulators were implemented with improved DA (distributed algorithm) to reduce hardware area and enhance speed performance. The VHSIC hardware description language (VHDC) simulation, synthesis and physical realization were implemented by EDA tools. It has been shown that compared with the existing design, the 2D IDCT ASIC design possesses the best timing performance.