A Novel 12-Bit 0.6-mW Two-Step Coarse-Fine Time-to-Digital Converter

Zhaoyuan Wang, Yeran Jin, Bo Zhou*

*此作品的通讯作者

科研成果: 期刊稿件文章同行评审

5 引用 (Scopus)

摘要

A novel two-step coarse-fine time-to-digital converter (TDC) is fabricated in 65-nm CMOS, with a relaxation oscillator based peak counter (ROC) for the coarse stage and a successive approximation analog-to-digital converter (SAR-ADC) for the fine stage. A reconfigurable 3-bit digital counter expands the dynamic range, and a high-precision 9-bit SAR-ADC ensures the resolution. The proposed ROC-ADC scheme conducts the time residence and the transfer linearity well for two-step quantization. Experimental results show that the presented 12-bit TDC achieves a high resolution less than 8 ps and a wide dynamic range up to 30 ns, with the differential nonlinearity (DNL) and integral nonlinearity (INL) values of 0.92 LSB and 1.07 LSB, respectively. The TDC consumes a low power of 0.6 mW from a 1-V supply, with the active area of 0.14 mm2.

源语言英语
页(从-至)4654-4658
页数5
期刊IEEE Transactions on Circuits and Systems II: Express Briefs
69
12
DOI
出版状态已出版 - 1 12月 2022

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Wang, Z., Jin, Y., & Zhou, B. (2022). A Novel 12-Bit 0.6-mW Two-Step Coarse-Fine Time-to-Digital Converter. IEEE Transactions on Circuits and Systems II: Express Briefs, 69(12), 4654-4658. https://doi.org/10.1109/TCSII.2022.3182158