摘要
This paper presents a high-throughput and size efficient buffer design method for an application specific NoC. The method firstly configures on chip buffer according with the mapping position of IP and the routing path of communication pairs, then computes the minimum value of buffer's size under NoC performance guarantee. Under the same buffer size, the experiments show that the method results in the 40% improvement of the throughput when compared the common input buffer design method.
| 源语言 | 英语 |
|---|---|
| 主期刊名 | 2012 International Conference on Systems and Informatics, ICSAI 2012 |
| 页 | 4-7 |
| 页数 | 4 |
| DOI | |
| 出版状态 | 已出版 - 2012 |
| 活动 | 2012 International Conference on Systems and Informatics, ICSAI 2012 - Yantai, 中国 期限: 19 5月 2012 → 20 5月 2012 |
出版系列
| 姓名 | 2012 International Conference on Systems and Informatics, ICSAI 2012 |
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会议
| 会议 | 2012 International Conference on Systems and Informatics, ICSAI 2012 |
|---|---|
| 国家/地区 | 中国 |
| 市 | Yantai |
| 时期 | 19/05/12 → 20/05/12 |
指纹
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Zhou, W., Liu, Z., Zhang, Y., Wang, S., & Liu, D. (2012). A high-throughput and size-efficient NoC buffer design method. 在 2012 International Conference on Systems and Informatics, ICSAI 2012 (页码 4-7). 文章 6223160 (2012 International Conference on Systems and Informatics, ICSAI 2012). https://doi.org/10.1109/ICSAI.2012.6223160