A high speed low complexity Reed-Solomon decoder for correcting errors and erasures

Jian Zhang; Guangrong Fan; Jingming Kuang; Hua Wang

doi:10.1109/ISCIT.2005.1567038

A high speed low complexity Reed-Solomon decoder for correcting errors and erasures

Jian Zhang^*, Guangrong Fan, Jingming Kuang, Hua Wang

^*此作品的通讯作者

信息与电子学院

Beijing Institute of Technology

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

1 引用（Scopus）

摘要

In this paper, a high speed low complexity architecture of Reed-Solomon(RS) code is developed to correct both errors and erasures based on the reformulation inversionless Berlekamp-Massey algorithm. In contrast to the inversionless Berlekamp-Massey architectures [7], the critical path delay of this decoding algorithm is smaller, and the architecture is extremely regular for VLSI implementation. The proposed decoder has been designed and synthesized for the Xilinx Virtex series FPGAs xcv600-5. The resource consumption is about 60%, and the data processing rates over 340Mbit/s is realized.

源语言	英语
主期刊名	ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings
页	976-979
页数	4
DOI	https://doi.org/10.1109/ISCIT.2005.1567038
出版状态	已出版 - 2005
活动	ISCIT 2005 - International Symposium on Communications and Information Technologies 2005 - Beijing, 中国期限: 12 10月 2005 → 14 10月 2005

出版系列

姓名	ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings
卷	I

会议

会议	ISCIT 2005 - International Symposium on Communications and Information Technologies 2005
国家/地区	中国
市	Beijing
时期	12/10/05 → 14/10/05

访问文件

10.1109/ISCIT.2005.1567038

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链接到 Scopus 的出版物

引用此

Zhang, J., Fan, G., Kuang, J., & Wang, H. (2005). A high speed low complexity Reed-Solomon decoder for correcting errors and erasures. 在 ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings (页码 976-979). 文章 1567038 (ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings; 卷 I). https://doi.org/10.1109/ISCIT.2005.1567038

@inproceedings{f782c44e41b649569c7ad941c797e6a7,

title = "A high speed low complexity Reed-Solomon decoder for correcting errors and erasures",

abstract = "In this paper, a high speed low complexity architecture of Reed-Solomon(RS) code is developed to correct both errors and erasures based on the reformulation inversionless Berlekamp-Massey algorithm. In contrast to the inversionless Berlekamp-Massey architectures [7], the critical path delay of this decoding algorithm is smaller, and the architecture is extremely regular for VLSI implementation. The proposed decoder has been designed and synthesized for the Xilinx Virtex series FPGAs xcv600-5. The resource consumption is about 60%, and the data processing rates over 340Mbit/s is realized.",

keywords = "Berlekamp-Massey algorithm, Erasure, Errata, Reed-Solomon(RS) Code, VLSI architectures",

author = "Jian Zhang and Guangrong Fan and Jingming Kuang and Hua Wang",

year = "2005",

doi = "10.1109/ISCIT.2005.1567038",

language = "English",

isbn = "0780395387",

series = "ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings",

pages = "976--979",

booktitle = "ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings",

note = "ISCIT 2005 - International Symposium on Communications and Information Technologies 2005 ; Conference date: 12-10-2005 Through 14-10-2005",

}

Zhang, J, Fan, G, Kuang, J & Wang, H 2005, A high speed low complexity Reed-Solomon decoder for correcting errors and erasures. 在 ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings., 1567038, ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings, 卷 I, 页码 976-979, ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Beijing, 中国, 12/10/05. https://doi.org/10.1109/ISCIT.2005.1567038

A high speed low complexity Reed-Solomon decoder for correcting errors and erasures. / Zhang, Jian; Fan, Guangrong; Kuang, Jingming 等.
ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings. 2005. 页码 976-979 1567038 (ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings; 卷 I).

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

TY - GEN

T1 - A high speed low complexity Reed-Solomon decoder for correcting errors and erasures

AU - Zhang, Jian

AU - Fan, Guangrong

AU - Kuang, Jingming

AU - Wang, Hua

PY - 2005

Y1 - 2005

N2 - In this paper, a high speed low complexity architecture of Reed-Solomon(RS) code is developed to correct both errors and erasures based on the reformulation inversionless Berlekamp-Massey algorithm. In contrast to the inversionless Berlekamp-Massey architectures [7], the critical path delay of this decoding algorithm is smaller, and the architecture is extremely regular for VLSI implementation. The proposed decoder has been designed and synthesized for the Xilinx Virtex series FPGAs xcv600-5. The resource consumption is about 60%, and the data processing rates over 340Mbit/s is realized.

AB - In this paper, a high speed low complexity architecture of Reed-Solomon(RS) code is developed to correct both errors and erasures based on the reformulation inversionless Berlekamp-Massey algorithm. In contrast to the inversionless Berlekamp-Massey architectures [7], the critical path delay of this decoding algorithm is smaller, and the architecture is extremely regular for VLSI implementation. The proposed decoder has been designed and synthesized for the Xilinx Virtex series FPGAs xcv600-5. The resource consumption is about 60%, and the data processing rates over 340Mbit/s is realized.

KW - Berlekamp-Massey algorithm

KW - Erasure

KW - Errata

KW - Reed-Solomon(RS) Code

KW - VLSI architectures

UR - http://www.scopus.com/inward/record.url?scp=33750105605&partnerID=8YFLogxK

U2 - 10.1109/ISCIT.2005.1567038

DO - 10.1109/ISCIT.2005.1567038

M3 - Conference contribution

AN - SCOPUS:33750105605

SN - 0780395387

SN - 9780780395381

T3 - ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings

SP - 976

EP - 979

BT - ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings

T2 - ISCIT 2005 - International Symposium on Communications and Information Technologies 2005

Y2 - 12 October 2005 through 14 October 2005

ER -

Zhang J, Fan G, Kuang J, Wang H. A high speed low complexity Reed-Solomon decoder for correcting errors and erasures. 在 ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings. 2005. 页码 976-979. 1567038. (ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings). doi: 10.1109/ISCIT.2005.1567038

A high speed low complexity Reed-Solomon decoder for correcting errors and erasures

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