A high speed low complexity Reed-Solomon decoder for correcting errors and erasures

Jian Zhang; Guangrong Fan; Jingming Kuang; Hua Wang

doi:10.1109/ISCIT.2005.1567038

A high speed low complexity Reed-Solomon decoder for correcting errors and erasures

Jian Zhang^*, Guangrong Fan, Jingming Kuang, Hua Wang

^*Corresponding author for this work

School of Information and Electronics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

In this paper, a high speed low complexity architecture of Reed-Solomon(RS) code is developed to correct both errors and erasures based on the reformulation inversionless Berlekamp-Massey algorithm. In contrast to the inversionless Berlekamp-Massey architectures [7], the critical path delay of this decoding algorithm is smaller, and the architecture is extremely regular for VLSI implementation. The proposed decoder has been designed and synthesized for the Xilinx Virtex series FPGAs xcv600-5. The resource consumption is about 60%, and the data processing rates over 340Mbit/s is realized.

Original language	English
Title of host publication	ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings
Pages	976-979
Number of pages	4
DOIs	https://doi.org/10.1109/ISCIT.2005.1567038
Publication status	Published - 2005
Event	ISCIT 2005 - International Symposium on Communications and Information Technologies 2005 - Beijing, China Duration: 12 Oct 2005 → 14 Oct 2005

Publication series

Name	ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings
Volume	I

Conference

Conference	ISCIT 2005 - International Symposium on Communications and Information Technologies 2005
Country/Territory	China
City	Beijing
Period	12/10/05 → 14/10/05

Keywords

Berlekamp-Massey algorithm
Erasure
Errata
Reed-Solomon(RS) Code
VLSI architectures

Access to Document

10.1109/ISCIT.2005.1567038

Cite this

Zhang, J., Fan, G., Kuang, J., & Wang, H. (2005). A high speed low complexity Reed-Solomon decoder for correcting errors and erasures. In ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings (pp. 976-979). Article 1567038 (ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings; Vol. I). https://doi.org/10.1109/ISCIT.2005.1567038

@inproceedings{f782c44e41b649569c7ad941c797e6a7,

title = "A high speed low complexity Reed-Solomon decoder for correcting errors and erasures",

abstract = "In this paper, a high speed low complexity architecture of Reed-Solomon(RS) code is developed to correct both errors and erasures based on the reformulation inversionless Berlekamp-Massey algorithm. In contrast to the inversionless Berlekamp-Massey architectures [7], the critical path delay of this decoding algorithm is smaller, and the architecture is extremely regular for VLSI implementation. The proposed decoder has been designed and synthesized for the Xilinx Virtex series FPGAs xcv600-5. The resource consumption is about 60%, and the data processing rates over 340Mbit/s is realized.",

keywords = "Berlekamp-Massey algorithm, Erasure, Errata, Reed-Solomon(RS) Code, VLSI architectures",

author = "Jian Zhang and Guangrong Fan and Jingming Kuang and Hua Wang",

year = "2005",

doi = "10.1109/ISCIT.2005.1567038",

language = "English",

isbn = "0780395387",

series = "ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings",

pages = "976--979",

booktitle = "ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings",

note = "ISCIT 2005 - International Symposium on Communications and Information Technologies 2005 ; Conference date: 12-10-2005 Through 14-10-2005",

}

Zhang, J, Fan, G, Kuang, J & Wang, H 2005, A high speed low complexity Reed-Solomon decoder for correcting errors and erasures. in ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings., 1567038, ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings, vol. I, pp. 976-979, ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Beijing, China, 12/10/05. https://doi.org/10.1109/ISCIT.2005.1567038

A high speed low complexity Reed-Solomon decoder for correcting errors and erasures. / Zhang, Jian; Fan, Guangrong; Kuang, Jingming et al.
ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings. 2005. p. 976-979 1567038 (ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings; Vol. I).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A high speed low complexity Reed-Solomon decoder for correcting errors and erasures

AU - Zhang, Jian

AU - Fan, Guangrong

AU - Kuang, Jingming

AU - Wang, Hua

PY - 2005

Y1 - 2005

N2 - In this paper, a high speed low complexity architecture of Reed-Solomon(RS) code is developed to correct both errors and erasures based on the reformulation inversionless Berlekamp-Massey algorithm. In contrast to the inversionless Berlekamp-Massey architectures [7], the critical path delay of this decoding algorithm is smaller, and the architecture is extremely regular for VLSI implementation. The proposed decoder has been designed and synthesized for the Xilinx Virtex series FPGAs xcv600-5. The resource consumption is about 60%, and the data processing rates over 340Mbit/s is realized.

AB - In this paper, a high speed low complexity architecture of Reed-Solomon(RS) code is developed to correct both errors and erasures based on the reformulation inversionless Berlekamp-Massey algorithm. In contrast to the inversionless Berlekamp-Massey architectures [7], the critical path delay of this decoding algorithm is smaller, and the architecture is extremely regular for VLSI implementation. The proposed decoder has been designed and synthesized for the Xilinx Virtex series FPGAs xcv600-5. The resource consumption is about 60%, and the data processing rates over 340Mbit/s is realized.

KW - Berlekamp-Massey algorithm

KW - Erasure

KW - Errata

KW - Reed-Solomon(RS) Code

KW - VLSI architectures

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U2 - 10.1109/ISCIT.2005.1567038

DO - 10.1109/ISCIT.2005.1567038

M3 - Conference contribution

AN - SCOPUS:33750105605

SN - 0780395387

SN - 9780780395381

T3 - ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings

SP - 976

EP - 979

BT - ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings

T2 - ISCIT 2005 - International Symposium on Communications and Information Technologies 2005

Y2 - 12 October 2005 through 14 October 2005

ER -

Zhang J, Fan G, Kuang J, Wang H. A high speed low complexity Reed-Solomon decoder for correcting errors and erasures. In ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings. 2005. p. 976-979. 1567038. (ISCIT 2005 - International Symposium on Communications and Information Technologies 2005, Proceedings). doi: 10.1109/ISCIT.2005.1567038

A high speed low complexity Reed-Solomon decoder for correcting errors and erasures

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