A 3.37-7.18 GHz Wideband PLL with Multi-core VCO in 180-nm CMOS

A 3.37-7.18 GHz charge pump phase-locked loop (CPPLL), employing a fast-startup wideband voltage-controlled oscillator (VCO) with four cores, is implemented in 1P6M 180-nm RF & Mixed Mode CMOS process. The proposed PLL utilizes a high-speed high-accuracy charge pump with an adjustable charging-discharging current of 0.2-1.6 mA. The multi-core VCO achieves phase noise performance of-122 dBc/Hz at 1 MHz offset of the 4th core, together with a successive approximation register based auto frequency control loop (SAR-AFC) which calibrates the frequency of the VCO for process, voltage and temperature (PVT) robustness consideration. A current-mode logic (CML) divider and a differential to single buffer are proposed as the prescaler, followed by a multi-modulus divider (MMD) and a delta-sigma modulator. The proposed PLL draws 42mA from 3.3V supply, featuring wideband and low phase noise.