TY - GEN
T1 - A 3.37-7.18 GHz Wideband PLL with Multi-core VCO in 180-nm CMOS
AU - Wang, Zuhang
AU - Zhou, Bo
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - A 3.37-7.18 GHz charge pump phase-locked loop (CPPLL), employing a fast-startup wideband voltage-controlled oscillator (VCO) with four cores, is implemented in 1P6M 180-nm RF & Mixed Mode CMOS process. The proposed PLL utilizes a high-speed high-accuracy charge pump with an adjustable charging-discharging current of 0.2-1.6 mA. The multi-core VCO achieves phase noise performance of-122 dBc/Hz at 1 MHz offset of the 4th core, together with a successive approximation register based auto frequency control loop (SAR-AFC) which calibrates the frequency of the VCO for process, voltage and temperature (PVT) robustness consideration. A current-mode logic (CML) divider and a differential to single buffer are proposed as the prescaler, followed by a multi-modulus divider (MMD) and a delta-sigma modulator. The proposed PLL draws 42mA from 3.3V supply, featuring wideband and low phase noise.
AB - A 3.37-7.18 GHz charge pump phase-locked loop (CPPLL), employing a fast-startup wideband voltage-controlled oscillator (VCO) with four cores, is implemented in 1P6M 180-nm RF & Mixed Mode CMOS process. The proposed PLL utilizes a high-speed high-accuracy charge pump with an adjustable charging-discharging current of 0.2-1.6 mA. The multi-core VCO achieves phase noise performance of-122 dBc/Hz at 1 MHz offset of the 4th core, together with a successive approximation register based auto frequency control loop (SAR-AFC) which calibrates the frequency of the VCO for process, voltage and temperature (PVT) robustness consideration. A current-mode logic (CML) divider and a differential to single buffer are proposed as the prescaler, followed by a multi-modulus divider (MMD) and a delta-sigma modulator. The proposed PLL draws 42mA from 3.3V supply, featuring wideband and low phase noise.
KW - charge pump
KW - multi-core
KW - phase noise
KW - phase-locked loop (PLL)
KW - successive approximation register (SAR)
KW - voltage-controlled oscillator (VCO)
KW - wideband
UR - http://www.scopus.com/inward/record.url?scp=85142416357&partnerID=8YFLogxK
U2 - 10.1109/ICCS56666.2022.9936380
DO - 10.1109/ICCS56666.2022.9936380
M3 - Conference contribution
AN - SCOPUS:85142416357
T3 - 2022 IEEE 4th International Conference on Circuits and Systems, ICCS 2022
SP - 135
EP - 139
BT - 2022 IEEE 4th International Conference on Circuits and Systems, ICCS 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 4th IEEE International Conference on Circuits and Systems, ICCS 2022
Y2 - 23 September 2022 through 26 September 2022
ER -
