3.4GS/s 3 bit phase digitizing ADC and DAC for DRFM

Min Zhang; Youtao Zhang; Xiaopeng Li; Ao Liu; Feng Qian

doi:10.1109/ASICON.2009.5351485

3.4GS/s 3 bit phase digitizing ADC and DAC for DRFM

Min Zhang^*, Youtao Zhang, Xiaopeng Li, Ao Liu, Feng Qian

^*此作品的通讯作者

材料学院

Nanjing Electronic Devices Institute

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

3 引用（Scopus）

摘要

This paper design and realize 3 bit phase digitizing analog-to-digital converter (ADC) and digital-to-analog converter (DAC) for Digital radio frequency memory (DRFM). The instantaneous bandwidth (IBW) of the DRFM is enhanced by high sampling rate. Test results show that the highest sampling rate is 3.4GS/s and the core power dissipation of ADC and DAC is 350mW and 300mW, respectively.

源语言	英语
主期刊名	ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
页	226-229
页数	4
DOI	https://doi.org/10.1109/ASICON.2009.5351485
出版状态	已出版 - 2009
活动	2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, 中国期限: 20 10月 2009 → 23 10月 2009

出版系列

姓名	ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

会议

会议	2009 8th IEEE International Conference on ASIC, ASICON 2009
国家/地区	中国
市	Changsha
时期	20/10/09 → 23/10/09

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10.1109/ASICON.2009.5351485

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引用此

Zhang, M., Zhang, Y., Li, X., Liu, A., & Qian, F. (2009). 3.4GS/s 3 bit phase digitizing ADC and DAC for DRFM. 在 ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC (页码 226-229). 文章 5351485 (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC). https://doi.org/10.1109/ASICON.2009.5351485

@inproceedings{46ee848e9e4c4f86b57cb7fb5b0d45e3,

title = "3.4GS/s 3 bit phase digitizing ADC and DAC for DRFM",

abstract = "This paper design and realize 3 bit phase digitizing analog-to-digital converter (ADC) and digital-to-analog converter (DAC) for Digital radio frequency memory (DRFM). The instantaneous bandwidth (IBW) of the DRFM is enhanced by high sampling rate. Test results show that the highest sampling rate is 3.4GS/s and the core power dissipation of ADC and DAC is 350mW and 300mW, respectively.",

keywords = "Analog-to-digital converter, Digital radio frequency memory, Digital-to-analog converter, Phase digitizing",

author = "Min Zhang and Youtao Zhang and Xiaopeng Li and Ao Liu and Feng Qian",

year = "2009",

doi = "10.1109/ASICON.2009.5351485",

language = "English",

isbn = "9781424438686",

series = "ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC",

pages = "226--229",

booktitle = "ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC",

note = "2009 8th IEEE International Conference on ASIC, ASICON 2009 ; Conference date: 20-10-2009 Through 23-10-2009",

}

Zhang, M, Zhang, Y, Li, X, Liu, A & Qian, F 2009, 3.4GS/s 3 bit phase digitizing ADC and DAC for DRFM. 在 ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC., 5351485, ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC, 页码 226-229, 2009 8th IEEE International Conference on ASIC, ASICON 2009, Changsha, 中国, 20/10/09. https://doi.org/10.1109/ASICON.2009.5351485

TY - GEN

T1 - 3.4GS/s 3 bit phase digitizing ADC and DAC for DRFM

AU - Zhang, Min

AU - Zhang, Youtao

AU - Li, Xiaopeng

AU - Liu, Ao

AU - Qian, Feng

PY - 2009

Y1 - 2009

N2 - This paper design and realize 3 bit phase digitizing analog-to-digital converter (ADC) and digital-to-analog converter (DAC) for Digital radio frequency memory (DRFM). The instantaneous bandwidth (IBW) of the DRFM is enhanced by high sampling rate. Test results show that the highest sampling rate is 3.4GS/s and the core power dissipation of ADC and DAC is 350mW and 300mW, respectively.

AB - This paper design and realize 3 bit phase digitizing analog-to-digital converter (ADC) and digital-to-analog converter (DAC) for Digital radio frequency memory (DRFM). The instantaneous bandwidth (IBW) of the DRFM is enhanced by high sampling rate. Test results show that the highest sampling rate is 3.4GS/s and the core power dissipation of ADC and DAC is 350mW and 300mW, respectively.

KW - Analog-to-digital converter

KW - Digital radio frequency memory

KW - Digital-to-analog converter

KW - Phase digitizing

UR - http://www.scopus.com/inward/record.url?scp=77949342967&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2009.5351485

DO - 10.1109/ASICON.2009.5351485

M3 - Conference contribution

AN - SCOPUS:77949342967

SN - 9781424438686

T3 - ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

SP - 226

EP - 229

BT - ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC

T2 - 2009 8th IEEE International Conference on ASIC, ASICON 2009

Y2 - 20 October 2009 through 23 October 2009

ER -

3.4GS/s 3 bit phase digitizing ADC and DAC for DRFM

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