3.4GS/s 3 bit phase digitizing ADC and DAC for DRFM

Min Zhang; Youtao Zhang; Xiaopeng Li; Ao Liu; Feng Qian

doi:10.1109/ASICON.2009.5351485

3.4GS/s 3 bit phase digitizing ADC and DAC for DRFM

Min Zhang^*, Youtao Zhang, Xiaopeng Li, Ao Liu, Feng Qian

^*Corresponding author for this work

School of Material Science and Engineering

Nanjing Electronic Devices Institute

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Citations (Scopus)

Abstract

This paper design and realize 3 bit phase digitizing analog-to-digital converter (ADC) and digital-to-analog converter (DAC) for Digital radio frequency memory (DRFM). The instantaneous bandwidth (IBW) of the DRFM is enhanced by high sampling rate. Test results show that the highest sampling rate is 3.4GS/s and the core power dissipation of ADC and DAC is 350mW and 300mW, respectively.

Original language	English
Title of host publication	ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
Pages	226-229
Number of pages	4
DOIs	https://doi.org/10.1109/ASICON.2009.5351485
Publication status	Published - 2009
Event	2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, China Duration: 20 Oct 2009 → 23 Oct 2009

Publication series

Name	ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Conference

Conference	2009 8th IEEE International Conference on ASIC, ASICON 2009
Country/Territory	China
City	Changsha
Period	20/10/09 → 23/10/09

Keywords

Analog-to-digital converter
Digital radio frequency memory
Digital-to-analog converter
Phase digitizing

Access to Document

10.1109/ASICON.2009.5351485

Cite this

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title = "3.4GS/s 3 bit phase digitizing ADC and DAC for DRFM",

abstract = "This paper design and realize 3 bit phase digitizing analog-to-digital converter (ADC) and digital-to-analog converter (DAC) for Digital radio frequency memory (DRFM). The instantaneous bandwidth (IBW) of the DRFM is enhanced by high sampling rate. Test results show that the highest sampling rate is 3.4GS/s and the core power dissipation of ADC and DAC is 350mW and 300mW, respectively.",

keywords = "Analog-to-digital converter, Digital radio frequency memory, Digital-to-analog converter, Phase digitizing",

author = "Min Zhang and Youtao Zhang and Xiaopeng Li and Ao Liu and Feng Qian",

year = "2009",

doi = "10.1109/ASICON.2009.5351485",

language = "English",

isbn = "9781424438686",

series = "ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC",

pages = "226--229",

booktitle = "ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC",

note = "2009 8th IEEE International Conference on ASIC, ASICON 2009 ; Conference date: 20-10-2009 Through 23-10-2009",

}

Zhang, M, Zhang, Y, Li, X, Liu, A & Qian, F 2009, 3.4GS/s 3 bit phase digitizing ADC and DAC for DRFM. in ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC., 5351485, ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC, pp. 226-229, 2009 8th IEEE International Conference on ASIC, ASICON 2009, Changsha, China, 20/10/09. https://doi.org/10.1109/ASICON.2009.5351485

3.4GS/s 3 bit phase digitizing ADC and DAC for DRFM. / Zhang, Min; Zhang, Youtao; Li, Xiaopeng et al.
ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC. 2009. p. 226-229 5351485 (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - 3.4GS/s 3 bit phase digitizing ADC and DAC for DRFM

AU - Zhang, Min

AU - Zhang, Youtao

AU - Li, Xiaopeng

AU - Liu, Ao

AU - Qian, Feng

PY - 2009

Y1 - 2009

N2 - This paper design and realize 3 bit phase digitizing analog-to-digital converter (ADC) and digital-to-analog converter (DAC) for Digital radio frequency memory (DRFM). The instantaneous bandwidth (IBW) of the DRFM is enhanced by high sampling rate. Test results show that the highest sampling rate is 3.4GS/s and the core power dissipation of ADC and DAC is 350mW and 300mW, respectively.

AB - This paper design and realize 3 bit phase digitizing analog-to-digital converter (ADC) and digital-to-analog converter (DAC) for Digital radio frequency memory (DRFM). The instantaneous bandwidth (IBW) of the DRFM is enhanced by high sampling rate. Test results show that the highest sampling rate is 3.4GS/s and the core power dissipation of ADC and DAC is 350mW and 300mW, respectively.

KW - Analog-to-digital converter

KW - Digital radio frequency memory

KW - Digital-to-analog converter

KW - Phase digitizing

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DO - 10.1109/ASICON.2009.5351485

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T3 - ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

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BT - ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC

T2 - 2009 8th IEEE International Conference on ASIC, ASICON 2009

Y2 - 20 October 2009 through 23 October 2009

ER -

3.4GS/s 3 bit phase digitizing ADC and DAC for DRFM

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Keywords

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