Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm

Yu Xie; Wen Yue Yu; Ning Zhang; He Chen; Yi Zhuang Xie

doi:10.1109/DFT59622.2023.10313538

Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm

Yu Xie^*, Wen Yue Yu, Ning Zhang, He Chen, Yi Zhuang Xie

^*Corresponding author for this work

School of Information and Electronics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

Circuits related to nuclear facilities and on-orbit circuits typically require fault-tolerant reinforcement to cope with harsh radiation environments. While the traditional fully Triple Modular Redundancy (TMR) method can effectively reinforce circuits, it suffers from the problems of large circuit area and high power consumption. To solve this problem, this paper proposes a Partial TMR method based on the HITS algorithm (Hyperlink-Induced Topic Search), which can effectively perform circuit fault tolerance. This method sorts the importance of triggers in the circuit based on the HITS algorithm and uses the Fault Interval Time (MTBF) of the Bi-Logic Cone model as the judgment criterion to determine the number of triggers that need to be redundantly designed under partial TMR. Some commonly used modules of an on-orbit processor were tested to verify the effectiveness of the proposed redundancy method in this paper. The experimental results show that the resource overhead can be reduced by at least 20% while achieving an MTBF of 99.9% under TMR.

Original language	English
Title of host publication	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023
Editors	Luca Cassano, Mihalis Psarakis, Marcello Traiola, Alberto Bosio
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350315004
DOIs	https://doi.org/10.1109/DFT59622.2023.10313538
Publication status	Published - 2023
Event	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 - Juan-Les-Pins, France Duration: 3 Oct 2023 → 5 Oct 2023

Publication series

Name	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
ISSN (Print)	2576-1501
ISSN (Electronic)	2765-933X

Conference

Conference	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023
Country/Territory	France
City	Juan-Les-Pins
Period	3/10/23 → 5/10/23

Keywords

ASIC
HITS
TMR
fault tolerant

Access to Document

10.1109/DFT59622.2023.10313538

Cite this

Xie, Y., Yu, W. Y., Zhang, N., Chen, H., & Xie, Y. Z. (2023). Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm. In L. Cassano, M. Psarakis, M. Traiola, & A. Bosio (Eds.), 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT59622.2023.10313538

Xie, Yu ; Yu, Wen Yue ; Zhang, Ning et al. / Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm. 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. editor / Luca Cassano ; Mihalis Psarakis ; Marcello Traiola ; Alberto Bosio. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

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title = "Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm",

abstract = "Circuits related to nuclear facilities and on-orbit circuits typically require fault-tolerant reinforcement to cope with harsh radiation environments. While the traditional fully Triple Modular Redundancy (TMR) method can effectively reinforce circuits, it suffers from the problems of large circuit area and high power consumption. To solve this problem, this paper proposes a Partial TMR method based on the HITS algorithm (Hyperlink-Induced Topic Search), which can effectively perform circuit fault tolerance. This method sorts the importance of triggers in the circuit based on the HITS algorithm and uses the Fault Interval Time (MTBF) of the Bi-Logic Cone model as the judgment criterion to determine the number of triggers that need to be redundantly designed under partial TMR. Some commonly used modules of an on-orbit processor were tested to verify the effectiveness of the proposed redundancy method in this paper. The experimental results show that the resource overhead can be reduced by at least 20% while achieving an MTBF of 99.9% under TMR.",

keywords = "ASIC, HITS, TMR, fault tolerant",

author = "Yu Xie and Yu, {Wen Yue} and Ning Zhang and He Chen and Xie, {Yi Zhuang}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 ; Conference date: 03-10-2023 Through 05-10-2023",

year = "2023",

doi = "10.1109/DFT59622.2023.10313538",

language = "English",

series = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Luca Cassano and Mihalis Psarakis and Marcello Traiola and Alberto Bosio",

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}

Xie, Y, Yu, WY, Zhang, N, Chen, H & Xie, YZ 2023, Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm. in L Cassano, M Psarakis, M Traiola & A Bosio (eds), 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, Institute of Electrical and Electronics Engineers Inc., 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023, Juan-Les-Pins, France, 3/10/23. https://doi.org/10.1109/DFT59622.2023.10313538

Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm. / Xie, Yu; Yu, Wen Yue; Zhang, Ning et al.
36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. ed. / Luca Cassano; Mihalis Psarakis; Marcello Traiola; Alberto Bosio. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm

AU - Xie, Yu

AU - Yu, Wen Yue

AU - Zhang, Ning

AU - Chen, He

AU - Xie, Yi Zhuang

PY - 2023

Y1 - 2023

N2 - Circuits related to nuclear facilities and on-orbit circuits typically require fault-tolerant reinforcement to cope with harsh radiation environments. While the traditional fully Triple Modular Redundancy (TMR) method can effectively reinforce circuits, it suffers from the problems of large circuit area and high power consumption. To solve this problem, this paper proposes a Partial TMR method based on the HITS algorithm (Hyperlink-Induced Topic Search), which can effectively perform circuit fault tolerance. This method sorts the importance of triggers in the circuit based on the HITS algorithm and uses the Fault Interval Time (MTBF) of the Bi-Logic Cone model as the judgment criterion to determine the number of triggers that need to be redundantly designed under partial TMR. Some commonly used modules of an on-orbit processor were tested to verify the effectiveness of the proposed redundancy method in this paper. The experimental results show that the resource overhead can be reduced by at least 20% while achieving an MTBF of 99.9% under TMR.

AB - Circuits related to nuclear facilities and on-orbit circuits typically require fault-tolerant reinforcement to cope with harsh radiation environments. While the traditional fully Triple Modular Redundancy (TMR) method can effectively reinforce circuits, it suffers from the problems of large circuit area and high power consumption. To solve this problem, this paper proposes a Partial TMR method based on the HITS algorithm (Hyperlink-Induced Topic Search), which can effectively perform circuit fault tolerance. This method sorts the importance of triggers in the circuit based on the HITS algorithm and uses the Fault Interval Time (MTBF) of the Bi-Logic Cone model as the judgment criterion to determine the number of triggers that need to be redundantly designed under partial TMR. Some commonly used modules of an on-orbit processor were tested to verify the effectiveness of the proposed redundancy method in this paper. The experimental results show that the resource overhead can be reduced by at least 20% while achieving an MTBF of 99.9% under TMR.

KW - ASIC

KW - HITS

KW - TMR

KW - fault tolerant

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U2 - 10.1109/DFT59622.2023.10313538

DO - 10.1109/DFT59622.2023.10313538

M3 - Conference contribution

AN - SCOPUS:85179008811

T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT

BT - 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023

A2 - Cassano, Luca

A2 - Psarakis, Mihalis

A2 - Traiola, Marcello

A2 - Bosio, Alberto

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023

Y2 - 3 October 2023 through 5 October 2023

ER -

Xie Y, Yu WY, Zhang N, Chen H , Xie YZ. Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm. In Cassano L, Psarakis M, Traiola M, Bosio A, editors, 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT). doi: 10.1109/DFT59622.2023.10313538

Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm

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