An efficient digital down converter architecture for wide band radar receiver

Ji Yang Yu*, Yang Li

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Citations (Scopus)

Abstract

This paper, the architecture and the implementation of an efficient digital down converter (DDC) processor for wide band radar receiver are presented. This architecture of the processor is based on the sampling technique in which the sampling frequency is 4 times as high as the intermediate frequency and the use of half band filter architecture. It avoids 3/4 the use of multiplications compared with the conventional architecture. The improved method decreases the complexity of computation, reduces the area and power of the processor. The efficient method is implemented in FPGA. Compared with the conventional method, resources are saved 82.78% and the power consumption is reduced about 100 mW. One design example is given and the results proved the validity and efficiency of the improved digital down converter architecture.

Original languageEnglish
Title of host publicationIET International Radar Conference 2009
Edition551 CP
DOIs
Publication statusPublished - 2009
EventIET International Radar Conference 2009 - Guilin, China
Duration: 20 Apr 200922 Apr 2009

Publication series

NameIET Conference Publications
Number551 CP

Conference

ConferenceIET International Radar Conference 2009
Country/TerritoryChina
CityGuilin
Period20/04/0922/04/09

Keywords

  • Digital down converter (DDC)
  • FPGA
  • Half band filter

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Cite this

Yu, J. Y., & Li, Y. (2009). An efficient digital down converter architecture for wide band radar receiver. In IET International Radar Conference 2009 (551 CP ed.). (IET Conference Publications; No. 551 CP). https://doi.org/10.1049/cp.2009.0097