Advanced des algorithm against differential power analysis and its hardware implementation

Huiping Jiang*, Rui Xu, Sheng Bao

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this article, the advanced DES algorithm against differential power analysis (DPA) is provided, based on the original model of DPA. The DES_DPA module is build according to the above principle, which the linear part of the module adopted the MASK technology for the specialty of the DES algorithm and the localizations of the storage. And its efficiency was explained from the view of DPA's principle. With 0.25μm CMOS technology library, the result showed that the gate count of DES_DPA module is about 1914, the maximize delay is 9.57 ns, and can be worked correctly under 100 MHz, so that it is well suited to the field of smart card and the information security.

Original languageEnglish
Title of host publicationProceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007
Pages316-320
Number of pages5
DOIs
Publication statusPublished - 2007
Event1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007 - Chengdu, China
Duration: 1 Nov 20073 Nov 2007

Publication series

NameProceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007

Conference

Conference1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007
Country/TerritoryChina
CityChengdu
Period1/11/073/11/07

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