A light-weighted viterbi decoder implemented by FPGA

Zhenzhi Wu; Shujuan Hou; Hai Li

doi:10.1109/IMCCC.2011.155

A light-weighted viterbi decoder implemented by FPGA

Zhenzhi Wu^*, Shujuan Hou, Hai Li

^*Corresponding author for this work

School of Information and Electronics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

In this paper, a light-weighted pipelined serial Viterbi Decoder is implemented for resource saving purpose. The trace back module of the decoder consumes fewer logical resources by employing a RAM-based Register Exchange architecture. All the metric and trace back bits are stored in the RAM to save logical resources. Synthesis results show that, the proposed architecture can save more than half of resource utilization than fabric IP core and has the minimum logic consumption than almost other schemes we can find with nearly no performance loss.

Original language	English
Title of host publication	Proceedings - 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control, IMCCC 2011
Pages	601-604
Number of pages	4
DOIs	https://doi.org/10.1109/IMCCC.2011.155
Publication status	Published - 2011
Event	1st International Conference on Instrumentation and Measurement, Computer, Communication and Control, IMCCC2011 - Beijing, China Duration: 21 Oct 2011 → 23 Oct 2011

Publication series

Name	Proceedings - 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control, IMCCC 2011

Conference

Conference	1st International Conference on Instrumentation and Measurement, Computer, Communication and Control, IMCCC2011
Country/Territory	China
City	Beijing
Period	21/10/11 → 23/10/11

Keywords

Register Exchange
Resource efficient
Viterbi Decoder

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10.1109/IMCCC.2011.155

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Wu, Z., Hou, S., & Li, H. (2011). A light-weighted viterbi decoder implemented by FPGA. In Proceedings - 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control, IMCCC 2011 (pp. 601-604). Article 6154180 (Proceedings - 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control, IMCCC 2011). https://doi.org/10.1109/IMCCC.2011.155

@inproceedings{d92b33555eca4ab8a550d644f7013daa,

title = "A light-weighted viterbi decoder implemented by FPGA",

abstract = "In this paper, a light-weighted pipelined serial Viterbi Decoder is implemented for resource saving purpose. The trace back module of the decoder consumes fewer logical resources by employing a RAM-based Register Exchange architecture. All the metric and trace back bits are stored in the RAM to save logical resources. Synthesis results show that, the proposed architecture can save more than half of resource utilization than fabric IP core and has the minimum logic consumption than almost other schemes we can find with nearly no performance loss.",

keywords = "Register Exchange, Resource efficient, Viterbi Decoder",

author = "Zhenzhi Wu and Shujuan Hou and Hai Li",

year = "2011",

doi = "10.1109/IMCCC.2011.155",

language = "English",

isbn = "9780769545196",

series = "Proceedings - 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control, IMCCC 2011",

pages = "601--604",

booktitle = "Proceedings - 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control, IMCCC 2011",

note = "1st International Conference on Instrumentation and Measurement, Computer, Communication and Control, IMCCC2011 ; Conference date: 21-10-2011 Through 23-10-2011",

}

Wu, Z, Hou, S & Li, H 2011, A light-weighted viterbi decoder implemented by FPGA. in Proceedings - 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control, IMCCC 2011., 6154180, Proceedings - 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control, IMCCC 2011, pp. 601-604, 1st International Conference on Instrumentation and Measurement, Computer, Communication and Control, IMCCC2011, Beijing, China, 21/10/11. https://doi.org/10.1109/IMCCC.2011.155

A light-weighted viterbi decoder implemented by FPGA. / Wu, Zhenzhi; Hou, Shujuan ; Li, Hai.
Proceedings - 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control, IMCCC 2011. 2011. p. 601-604 6154180 (Proceedings - 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control, IMCCC 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, a light-weighted pipelined serial Viterbi Decoder is implemented for resource saving purpose. The trace back module of the decoder consumes fewer logical resources by employing a RAM-based Register Exchange architecture. All the metric and trace back bits are stored in the RAM to save logical resources. Synthesis results show that, the proposed architecture can save more than half of resource utilization than fabric IP core and has the minimum logic consumption than almost other schemes we can find with nearly no performance loss.

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KW - Resource efficient

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Wu Z, Hou S , Li H. A light-weighted viterbi decoder implemented by FPGA. In Proceedings - 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control, IMCCC 2011. 2011. p. 601-604. 6154180. (Proceedings - 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control, IMCCC 2011). doi: 10.1109/IMCCC.2011.155

A light-weighted viterbi decoder implemented by FPGA

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