一种动态可配置二维CFAR处理器的设计与实现

Wei Gao; Hao Yang; Rong Kun Jiang; Fang Xie; Zhe Zhou; Xiao Hua Wang

doi:10.15918/j.tbit1001-0645.2018.517

一种动态可配置二维CFAR处理器的设计与实现

Translated title of the contribution: Design and Implementation of a Runtime-Configurable Two-Dimensional CFAR Processor

Wei Gao, Hao Yang, Rong Kun Jiang, Fang Xie, Zhe Zhou, Xiao Hua Wang^*

^*Corresponding author for this work

School of Integrated Circuits and Electronics

Beijing Institute of Technology

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

A hardware architecture of runtime-configurable two-dimensional constant false alarm rate CFAR processor was proposed based on FPGA to improve the algorithm speed for multi-scenario. This processor was designed to implement four pipeline architecture operations, cell averaging (CA), greatest of (GO), smallest of (SO) and ordered statistics (OS), for two-dimensional rectangular window (2D-RW) detectors. Also, controlling correlative parameters, this processor could make the reference window size, guard window size and detector type configurable. Test results show that, for 256×512 points data, the computation time of each detector in the processor is less than 3ms, and the relative error of detection threshold is no more than 0.1%, validating its better detection ability for two-dimensional radar data.

Translated title of the contribution	Design and Implementation of a Runtime-Configurable Two-Dimensional CFAR Processor
Original language	Chinese (Traditional)
Pages (from-to)	797-802
Number of pages	6
Journal	Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology
Volume	40
Issue number	7
DOIs	https://doi.org/10.15918/j.tbit1001-0645.2018.517
Publication status	Published - 1 Jul 2020

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title = "一种动态可配置二维CFAR处理器的设计与实现",

abstract = "A hardware architecture of runtime-configurable two-dimensional constant false alarm rate CFAR processor was proposed based on FPGA to improve the algorithm speed for multi-scenario. This processor was designed to implement four pipeline architecture operations, cell averaging (CA), greatest of (GO), smallest of (SO) and ordered statistics (OS), for two-dimensional rectangular window (2D-RW) detectors. Also, controlling correlative parameters, this processor could make the reference window size, guard window size and detector type configurable. Test results show that, for 256×512 points data, the computation time of each detector in the processor is less than 3ms, and the relative error of detection threshold is no more than 0.1%, validating its better detection ability for two-dimensional radar data.",

keywords = "Field programmable gate array (FPGA), Radar target detection, Runtime-configurable, Two-dimensional constant false alarm rate",

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AU - Gao, Wei

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AU - Jiang, Rong Kun

AU - Xie, Fang

AU - Zhou, Zhe

AU - Wang, Xiao Hua

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AB - A hardware architecture of runtime-configurable two-dimensional constant false alarm rate CFAR processor was proposed based on FPGA to improve the algorithm speed for multi-scenario. This processor was designed to implement four pipeline architecture operations, cell averaging (CA), greatest of (GO), smallest of (SO) and ordered statistics (OS), for two-dimensional rectangular window (2D-RW) detectors. Also, controlling correlative parameters, this processor could make the reference window size, guard window size and detector type configurable. Test results show that, for 256×512 points data, the computation time of each detector in the processor is less than 3ms, and the relative error of detection threshold is no more than 0.1%, validating its better detection ability for two-dimensional radar data.

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一种动态可配置二维CFAR处理器的设计与实现

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