Word length Optimization Method for Radix-2^k Fixed-Point Pipeline FFT Processors

In order to overcome the disadvantages of higher logic resource occupancy when implementing a radix-2^k fixed-point pipelined FFT processor with single-path delay feedback architecture, the word length optimization method is proposed. Under the premise of the output signal quantization noise ratio (SQNR) which needs to be achieved, the optimized word length required for each butterfly operation stage can be obtained by direct formula calculation based on theoretical derivation and mathematical modeling, providing the theoretical basis for the word length configuration for the implementation of the fixed-point pipelined FFT processor. Compared with some previous works, the fixed-point pipeline FFT processor realized with the proposed method has the advantages of lower storage resource occupation while ensuring the processing precision.