摘要
Solving bottleneck of bus is becoming a challenging task in the design of parallel radar signal processing area. This paper has introduced a novel technology called active cache to solve this problem. By actively inserting the cache code into programs, the system will cache the remote data to local before using it. This approach is applied to the UTDSP benchmark suites, giving a good experiment result on an embedded signal processing system of four TigerSHARC101 DSPs.
| 源语言 | 英语 |
|---|---|
| 主期刊名 | 8th International Conference on Signal Processing, ICSP 2006 |
| DOI | |
| 出版状态 | 已出版 - 2007 |
| 活动 | 8th International Conference on Signal Processing, ICSP 2006 - Guilin, 中国 期限: 16 11月 2006 → 20 11月 2006 |
出版系列
| 姓名 | International Conference on Signal Processing Proceedings, ICSP |
|---|---|
| 卷 | 4 |
会议
| 会议 | 8th International Conference on Signal Processing, ICSP 2006 |
|---|---|
| 国家/地区 | 中国 |
| 市 | Guilin |
| 时期 | 16/11/06 → 20/11/06 |
指纹
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Qin, F., Wang, Z., & Long, T. (2007). Using active cache to solve the bottleneck of bus in the parallel Radar signal process system. 在 8th International Conference on Signal Processing, ICSP 2006 文章 4129688 (International Conference on Signal Processing Proceedings, ICSP; 卷 4). https://doi.org/10.1109/ICOSP.2006.345996