Three-level Memory Access Architecture for FPGA-based Real-time Remote Sensing Image Processing System

Recently, extensive convolutional neural network (CNN)-based methods have been used for real-time remote sensing image processing system. However, the huge storage requirement for model and input image bring a great challenge to hardware implement. In this paper, we propose a three-level memory access architecture for FPGA-based real-time remote sensing image processing system to meet the storage requirement. Moreover, in the proposed architecture, the computational throughput is well matched to the storage bandwidth, which improve the efficiency of arithmetic processing on the hardware platform. In the experiment, we applied the architecture to the hardware implementation of CNN, and implement on Xilinx ZYNQ xc7z035 platform. Our design is evaluated on a main part of the modified YOLOv2 framework [1]. The experimental results demonstrate that this design can access the off-chip memory efficiently, and can provide the required parameters and input data for the CNN on-chip pipeline processing.