Methods to improve system verification efficiency in FPGA-based spaceborne SAR image processing system

With the rapid development of satellite-based signal processing technologies comes the widespread deployment of SAR image processing systems in spaceborne applications, many of which are implemented as FPGA-based systems thanks to the introduction of modern programmable devices with high capacity and complexity. However, as raw data of SAR satellites grow in size and bandwidth the effective implementation and especially the efficient system verification are emerging as the bottleneck in the development of FPGA-based SAR image processing systems. This paper proposes methods in the verification phase of FPGA-based SAR processing system development which on one hand increases the verification speed during simulations and on the other addresses the hardware/Matlab mismatch issue through comparison of floating point numbers on grounds of error analysis from a mathematical approach. Actual development process indicate that the proposed methods guarantee quick design convergence, and test results on real hardware confirm that the SAR image processing system offers acceptable quality of image output.