TY - CONF
T1 - Interface conversion and extension based on FPGA in high-speed real-time signal processing system
AU - Sun, Hao
AU - Chen, Fang
AU - Hu, Shanqing
AU - Li, Xingming
AU - Sun, Yujie
PY - 2015
Y1 - 2015
N2 - The radar systems have been so significant for both civil use and national defense, and adopting localized processor has become critical for a country, especially for the area related to the national defense. In this paper, we utilize localized BWDSP100 as the main processor, and implement a high-speed and real-time signal processing system by using BWDSP100 + FPGA framework. We use FPGA to realize the interface conversions and extensions, which enhance the reading bandwidth of the DDR2 interface from 235MB/s to 562MB/s. Besides that, we also integrate highspeed serial buses, such as PCIe interface of 243MB/s and SRIO interface of 344MB/s, for communications in or between boards. The system has been used in several projects, and works well.
AB - The radar systems have been so significant for both civil use and national defense, and adopting localized processor has become critical for a country, especially for the area related to the national defense. In this paper, we utilize localized BWDSP100 as the main processor, and implement a high-speed and real-time signal processing system by using BWDSP100 + FPGA framework. We use FPGA to realize the interface conversions and extensions, which enhance the reading bandwidth of the DDR2 interface from 235MB/s to 562MB/s. Besides that, we also integrate highspeed serial buses, such as PCIe interface of 243MB/s and SRIO interface of 344MB/s, for communications in or between boards. The system has been used in several projects, and works well.
KW - BWDSP100
KW - DSP+FPGA framework
KW - High-speed real-time signal processing
KW - Localizable DSP
UR - http://www.scopus.com/inward/record.url?scp=84973582923&partnerID=8YFLogxK
M3 - Paper
AN - SCOPUS:84973582923
T2 - IET International Radar Conference 2015
Y2 - 14 October 2015 through 16 October 2015
ER -