Implementing programming pre-triggering and expanding capacity of storage using FIFO in series

To satisfy high speed large capacity of data buffering in modern high-resolution radar and pre-triggering sampling in passive radar or passive time-of-arrival-location system, this paper presents an architecture to expand the buffering capacity. The pre-triggering function using multi first input first output (FIFO) in series is realized, the timing between two level FIFOs is analyzed, and a method for setting the programmable flag in FIFO is given. Practice demonstrates that, the capacity of buffering amounts to 2 MB, and the number of pre-triggering amounts to 1 MB. Further more, the functions can be switched by field programmable gate array (FPGA). The configuration is also fit for other kinds of FIFO having programmable flag.