Design of quaternary logic circuits based on multiple-valued current mode

In order to improve the performance of arithmetic VLSI system, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode (MVCM) by using dynamic source-coupled logic (SCL). Its key components, the comparator and the output generator, are both based on differential-pair circuit (DPC), and the latter is constructed by using structure of DPC trees. The pre-charge evaluates logic style, makes steady current flow cut off, thereby greatly saving the power dissipation. The combination of multiple-valued source-coupled logic and differential-pair circuit makes its power lower and its structure more compact. The performance is evaluated by HSPICE simulation with 0.18 μm CMOS technology. The power dissipation, transistor numbers and delay are superior to corresponding binary CMOS implementation. Multiple-valued logic is the potential solution for the high performance arithmetic VLSI system in the future.