Design of quaternary logic circuits based on multiple-valued current mode

Haixia Wu*, Shunan Zhong, Qilong Cai, Qianbin Xia, Yueyang Chen

*此作品的通讯作者

科研成果: 书/报告/会议事项章节会议稿件同行评审

1 引用 (Scopus)

摘要

In order to improve the performance of arithmetic VLSI system, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode (MVCM) by using dynamic source-coupled logic (SCL). Its key components, the comparator and the output generator, are both based on differential-pair circuit (DPC), and the latter is constructed by using structure of DPC trees. The pre-charge evaluates logic style, makes steady current flow cut off, thereby greatly saving the power dissipation. The combination of multiple-valued source-coupled logic and differential-pair circuit makes its power lower and its structure more compact. The performance is evaluated by HSPICE simulation with 0.18 μm CMOS technology. The power dissipation, transistor numbers and delay are superior to corresponding binary CMOS implementation. Multiple-valued logic is the potential solution for the high performance arithmetic VLSI system in the future.

源语言英语
主期刊名Electrical, Information Engineering and Mechatronics 2011 - Proceedings of the 2011 International Conference on Electrical, Information Engineering and Mechatronics, EIEM 2011
479-488
页数10
DOI
出版状态已出版 - 2012
活动2011 International Conference on Electrical, Information Engineering and Mechatronics, EIEM 2011 - Jiaozuo, Henan, 中国
期限: 23 12月 201125 12月 2011

出版系列

姓名Lecture Notes in Electrical Engineering
138 LNEE
ISSN(印刷版)1876-1100
ISSN(电子版)1876-1119

会议

会议2011 International Conference on Electrical, Information Engineering and Mechatronics, EIEM 2011
国家/地区中国
Jiaozuo, Henan
时期23/12/1125/12/11

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